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Issue 1886263004: Subzero. ARM32. Implements vector select. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addresses comments. Created 4 years, 8 months ago
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1 ; Test that we handle select on vectors. 1 ; Test that we handle select on vectors.
2 2
3 ; TODO(eholk): This test will need to be updated once comparison is no longer
4 ; scalarized.
5
6 ; REQUIRES: allow_dump 3 ; REQUIRES: allow_dump
7 4
8 ; Compile using standalone assembler. 5 ; Compile using standalone assembler.
9 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ 6 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
10 ; RUN: | FileCheck %s --check-prefix=ASM 7 ; RUN: | FileCheck %s --check-prefix=ASM
11 8
9 ; Show bytes in assembled standalone code.
10 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
11 ; RUN: --args -O2 --reg-use=s20 | FileCheck %s --check-prefix=DIS
12
13 ; Compile using integrated assembler.
14 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
15 ; RUN: --reg-use=s20 \
16 ; RUN: | FileCheck %s --check-prefix=IASM
17
18 ; Show bytes in assembled integrated code.
19 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
20 ; RUN: --args -O2 --reg-use=s20 | FileCheck %s --check-prefix=DIS
21
12 define internal <4 x float> @select4float(<4 x i1> %s, <4 x float> %a, 22 define internal <4 x float> @select4float(<4 x i1> %s, <4 x float> %a,
13 <4 x float> %b) { 23 <4 x float> %b) {
14 ; ASM-LABEL:select4float: 24 ; ASM-LABEL:select4float:
15 ; DIS-LABEL:00000000 <select4float>: 25 ; DIS-LABEL:00000000 <select4float>:
26 ; IASM-LABEL:select4float:
16 27
17 entry: 28 entry:
18 %res = select <4 x i1> %s, <4 x float> %a, <4 x float> %b 29 %res = select <4 x i1> %s, <4 x float> %a, <4 x float> %b
19 30
20 ; ASM:» # q3 = def.pseudo 31 ; ASM: vshl.u32 [[M:.*]], {{.*}}, #31
21 ; ASM-NEXT:» vmov.s8»r0, d0[0] 32 ; ASM-NEXT: vshr.s32 [[M:.*]], {{.*}}, #31
22 ; ASM-NEXT:» vmov.f32» s16, s4 33 ; ASM-NEXT: vbsl.i32 [[M]], {{.*}}
23 ; ASM-NEXT:» vmov.f32» s17, s8 34 ; DIS: 0: f2bf0550
24 ; ASM-NEXT:» tst» r0, #1 35 ; DIS-NEXT: 4: f2a10050
25 ; ASM-NEXT:» vmovne.f32» s17, s16 36 ; DIS-NEXT: 8: f3120154
26 ; ASM-NEXT:» vmov.f32» s12, s17 37 ; IASM-NOT: vshl
27 ; ASM-NEXT:» vmov.s8»r0, d0[4] 38 ; IASM-NOT: vshr
28 ; ASM-NEXT:» vmov.f32» s16, s5 39 ; IASM-NOT: vbsl
29 ; ASM-NEXT:» vmov.f32» s17, s9
30 ; ASM-NEXT:» tst» r0, #1
31 ; ASM-NEXT:» vmovne.f32» s17, s16
32 ; ASM-NEXT:» vmov.f32» s13, s17
33 ; ASM-NEXT:» vmov.s8»r0, d1[0]
34 ; ASM-NEXT:» vmov.f32» s16, s6
35 ; ASM-NEXT:» vmov.f32» s17, s10
36 ; ASM-NEXT:» tst» r0, #1
37 ; ASM-NEXT:» vmovne.f32» s17, s16
38 ; ASM-NEXT:» vmov.f32» s14, s17
39 ; ASM-NEXT:» vmov.s8»r0, d1[4]
40 ; ASM-NEXT:» vmov.f32» s4, s7
41 ; ASM-NEXT:» vmov.f32» s8, s11
42 ; ASM-NEXT:» tst» r0, #1
43 ; ASM-NEXT:» vmovne.f32» s8, s4
44 ; ASM-NEXT:» vmov.f32» s15, s8
45 ; ASM-NEXT:» vmov.f32» q0, q3
46 ; ASM-NEXT:» vpop» {s16, s17}
47 ; ASM-NEXT:» # s16 = def.pseudo
48 ; ASM-NEXT:» # s17 = def.pseudo
49 ; ASM-NEXT:» bx» lr
50 40
51 ret <4 x float> %res 41 ret <4 x float> %res
52 } 42 }
53 43
54 define internal <4 x i32> @select4i32(<4 x i1> %s, <4 x i32> %a, <4 x i32> %b) { 44 define internal <4 x i32> @select4i32(<4 x i1> %s, <4 x i32> %a, <4 x i32> %b) {
55 ; ASM-LABEL:select4i32: 45 ; ASM-LABEL:select4i32:
56 ; DIS-LABEL:00000000 <select4i32>: 46 ; DIS-LABEL:00000010 <select4i32>:
47 ; IASM-LABEL:select4i32:
57 48
58 entry: 49 entry:
59 %res = select <4 x i1> %s, <4 x i32> %a, <4 x i32> %b 50 %res = select <4 x i1> %s, <4 x i32> %a, <4 x i32> %b
60 51
61 ; ASM:» # q3 = def.pseudo 52 ; ASM: vshl.u32 [[M:.*]], {{.*}}, #31
62 ; ASM-NEXT:» vmov.s8»r0, d0[0] 53 ; ASM-NEXT: vshr.s32 [[M:.*]], {{.*}}, #31
63 ; ASM-NEXT:» vmov.32»r1, d2[0] 54 ; ASM-NEXT: vbsl.i32 [[M]], {{.*}}
64 ; ASM-NEXT:» vmov.32»r2, d4[0] 55 ; DIS: 10: f2bf0550
65 ; ASM-NEXT:» tst» r0, #1 56 ; DIS-NEXT: 14: f2a10050
66 ; ASM-NEXT:» movne» r2, r1 57 ; DIS_NEXT: 18: f3120154
67 ; ASM-NEXT:» vmov.32»d6[0], r2 58 ; IASM-NOT: vshl
68 ; ASM-NEXT:» vmov.s8»r0, d0[4] 59 ; IASM-NOT: vshr
69 ; ASM-NEXT:» vmov.32»r1, d2[1] 60 ; IASM-NOT: vbsl
70 ; ASM-NEXT:» vmov.32»r2, d4[1]
71 ; ASM-NEXT:» tst» r0, #1
72 ; ASM-NEXT:» movne» r2, r1
73 ; ASM-NEXT:» vmov.32»d6[1], r2
74 ; ASM-NEXT:» vmov.s8»r0, d1[0]
75 ; ASM-NEXT:» vmov.32»r1, d3[0]
76 ; ASM-NEXT:» vmov.32»r2, d5[0]
77 ; ASM-NEXT:» tst» r0, #1
78 ; ASM-NEXT:» movne» r2, r1
79 ; ASM-NEXT:» vmov.32»d7[0], r2
80 ; ASM-NEXT:» vmov.s8»r0, d1[4]
81 ; ASM-NEXT:» vmov.32»r1, d3[1]
82 ; ASM-NEXT:» vmov.32»r2, d5[1]
83 ; ASM-NEXT:» tst» r0, #1
84 ; ASM-NEXT:» movne» r2, r1
85 ; ASM-NEXT:» vmov.32»d7[1], r2
86 ; ASM-NEXT:» vmov.i32» q0, q3
87 ; ASM-NEXT:» bx» lr
88 61
89 ret <4 x i32> %res 62 ret <4 x i32> %res
90 } 63 }
91 64
92 define internal <8 x i16> @select8i16(<8 x i1> %s, <8 x i16> %a, <8 x i16> %b) { 65 define internal <8 x i16> @select8i16(<8 x i1> %s, <8 x i16> %a, <8 x i16> %b) {
93 ; ASM-LABEL:select8i16: 66 ; ASM-LABEL:select8i16:
94 ; DIS-LABEL:00000000 <select8i16>: 67 ; DIS-LABEL:00000020 <select8i16>:
68 ; IASM-LABEL:select8i16:
95 69
96 entry: 70 entry:
97 %res = select <8 x i1> %s, <8 x i16> %a, <8 x i16> %b 71 %res = select <8 x i1> %s, <8 x i16> %a, <8 x i16> %b
98 72
99 ; ASM:» # q3 = def.pseudo 73 ; ASM: vshl.u16 [[M:.*]], {{.*}}, #15
100 ; ASM-NEXT:» vmov.s8»r0, d0[0] 74 ; ASM-NEXT: vshr.s16 [[M:.*]], {{.*}}, #15
101 ; ASM-NEXT:» vmov.s16» r1, d2[0] 75 ; ASM-NEXT: vbsl.i16 [[M]], {{.*}}
102 ; ASM-NEXT:» vmov.s16» r2, d4[0] 76 ; DIS: 20: f29f0550
103 ; ASM-NEXT:» tst» r0, #1 77 ; DIS-NEXT: 24: f2910050
104 ; ASM-NEXT:» movne» r2, r1 78 ; DIS-NEXT: 28: f3120154
105 ; ASM-NEXT:» vmov.16»d6[0], r2 79 ; IASM-NOT: vshl
106 ; ASM-NEXT:» vmov.s8»r0, d0[2] 80 ; IASM-NOT: vshr
107 ; ASM-NEXT:» vmov.s16» r1, d2[1] 81 ; IASM-NOT: vbsl
108 ; ASM-NEXT:» vmov.s16» r2, d4[1]
109 ; ASM-NEXT:» tst» r0, #1
110 ; ASM-NEXT:» movne» r2, r1
111 ; ASM-NEXT:» vmov.16»d6[1], r2
112 ; ASM-NEXT:» vmov.s8»r0, d0[4]
113 ; ASM-NEXT:» vmov.s16» r1, d2[2]
114 ; ASM-NEXT:» vmov.s16» r2, d4[2]
115 ; ASM-NEXT:» tst» r0, #1
116 ; ASM-NEXT:» movne» r2, r1
117 ; ASM-NEXT:» vmov.16»d6[2], r2
118 ; ASM-NEXT:» vmov.s8»r0, d0[6]
119 ; ASM-NEXT:» vmov.s16» r1, d2[3]
120 ; ASM-NEXT:» vmov.s16» r2, d4[3]
121 ; ASM-NEXT:» tst» r0, #1
122 ; ASM-NEXT:» movne» r2, r1
123 ; ASM-NEXT:» vmov.16»d6[3], r2
124 ; ASM-NEXT:» vmov.s8»r0, d1[0]
125 ; ASM-NEXT:» vmov.s16» r1, d3[0]
126 ; ASM-NEXT:» vmov.s16» r2, d5[0]
127 ; ASM-NEXT:» tst» r0, #1
128 ; ASM-NEXT:» movne» r2, r1
129 ; ASM-NEXT:» vmov.16»d7[0], r2
130 ; ASM-NEXT:» vmov.s8»r0, d1[2]
131 ; ASM-NEXT:» vmov.s16» r1, d3[1]
132 ; ASM-NEXT:» vmov.s16» r2, d5[1]
133 ; ASM-NEXT:» tst» r0, #1
134 ; ASM-NEXT:» movne» r2, r1
135 ; ASM-NEXT:» vmov.16»d7[1], r2
136 ; ASM-NEXT:» vmov.s8»r0, d1[4]
137 ; ASM-NEXT:» vmov.s16» r1, d3[2]
138 ; ASM-NEXT:» vmov.s16» r2, d5[2]
139 ; ASM-NEXT:» tst» r0, #1
140 ; ASM-NEXT:» movne» r2, r1
141 ; ASM-NEXT:» vmov.16»d7[2], r2
142 ; ASM-NEXT:» vmov.s8»r0, d1[6]
143 ; ASM-NEXT:» vmov.s16» r1, d3[3]
144 ; ASM-NEXT:» vmov.s16» r2, d5[3]
145 ; ASM-NEXT:» tst» r0, #1
146 ; ASM-NEXT:» movne» r2, r1
147 ; ASM-NEXT:» vmov.16»d7[3], r2
148 ; ASM-NEXT:» vmov.i16» q0, q3
149 ; ASM-NEXT:» bx» lr
150 82
151 ret <8 x i16> %res 83 ret <8 x i16> %res
152 } 84 }
153 85
154 define internal <16 x i8> @select16i8(<16 x i1> %s, <16 x i8> %a, 86 define internal <16 x i8> @select16i8(<16 x i1> %s, <16 x i8> %a,
155 <16 x i8> %b) { 87 <16 x i8> %b) {
156 ; ASM-LABEL:select16i8: 88 ; ASM-LABEL:select16i8:
157 ; DIS-LABEL:00000000 <select16i8>: 89 ; DIS-LABEL:00000030 <select16i8>:
90 ; IASM-LABEL:select16i8:
158 91
159 entry: 92 entry:
160 %res = select <16 x i1> %s, <16 x i8> %a, <16 x i8> %b 93 %res = select <16 x i1> %s, <16 x i8> %a, <16 x i8> %b
161 94
162 ; ASM:» # q3 = def.pseudo 95 ; ASM: vshl.u8 [[M:.*]], {{.*}}, #7
163 ; ASM-NEXT:» vmov.s8»r0, d0[0] 96 ; ASM-NEXT: vshr.s8 [[M:.*]], {{.*}}, #7
164 ; ASM-NEXT:» vmov.s8»r1, d2[0] 97 ; ASM-NEXT: vbsl.i8 [[M]], {{.*}}
165 ; ASM-NEXT:» vmov.s8»r2, d4[0] 98 ; DIS: 30: f28f0550
166 ; ASM-NEXT:» tst» r0, #1 99 ; DIS-NEXT: 34: f2890050
167 ; ASM-NEXT:» movne» r2, r1 100 ; DIS-NEXT: 38: f3120154
168 ; ASM-NEXT:» vmov.8» d6[0], r2 101 ; IASM-NOT: vshl
169 ; ASM-NEXT:» vmov.s8»r0, d0[1] 102 ; IASM-NOT: vshr
170 ; ASM-NEXT:» vmov.s8»r1, d2[1] 103 ; IASM-NOT: vbsl
171 ; ASM-NEXT:» vmov.s8»r2, d4[1]
172 ; ASM-NEXT:» tst» r0, #1
173 ; ASM-NEXT:» movne» r2, r1
174 ; ASM-NEXT:» vmov.8» d6[1], r2
175 ; ASM-NEXT:» vmov.s8»r0, d0[2]
176 ; ASM-NEXT:» vmov.s8»r1, d2[2]
177 ; ASM-NEXT:» vmov.s8»r2, d4[2]
178 ; ASM-NEXT:» tst» r0, #1
179 ; ASM-NEXT:» movne» r2, r1
180 ; ASM-NEXT:» vmov.8» d6[2], r2
181 ; ASM-NEXT:» vmov.s8»r0, d0[3]
182 ; ASM-NEXT:» vmov.s8»r1, d2[3]
183 ; ASM-NEXT:» vmov.s8»r2, d4[3]
184 ; ASM-NEXT:» tst» r0, #1
185 ; ASM-NEXT:» movne» r2, r1
186 ; ASM-NEXT:» vmov.8» d6[3], r2
187 ; ASM-NEXT:» vmov.s8»r0, d0[4]
188 ; ASM-NEXT:» vmov.s8»r1, d2[4]
189 ; ASM-NEXT:» vmov.s8»r2, d4[4]
190 ; ASM-NEXT:» tst» r0, #1
191 ; ASM-NEXT:» movne» r2, r1
192 ; ASM-NEXT:» vmov.8» d6[4], r2
193 ; ASM-NEXT:» vmov.s8»r0, d0[5]
194 ; ASM-NEXT:» vmov.s8»r1, d2[5]
195 ; ASM-NEXT:» vmov.s8»r2, d4[5]
196 ; ASM-NEXT:» tst» r0, #1
197 ; ASM-NEXT:» movne» r2, r1
198 ; ASM-NEXT:» vmov.8» d6[5], r2
199 ; ASM-NEXT:» vmov.s8»r0, d0[6]
200 ; ASM-NEXT:» vmov.s8»r1, d2[6]
201 ; ASM-NEXT:» vmov.s8»r2, d4[6]
202 ; ASM-NEXT:» tst» r0, #1
203 ; ASM-NEXT:» movne» r2, r1
204 ; ASM-NEXT:» vmov.8» d6[6], r2
205 ; ASM-NEXT:» vmov.s8»r0, d0[7]
206 ; ASM-NEXT:» vmov.s8»r1, d2[7]
207 ; ASM-NEXT:» vmov.s8»r2, d4[7]
208 ; ASM-NEXT:» tst» r0, #1
209 ; ASM-NEXT:» movne» r2, r1
210 ; ASM-NEXT:» vmov.8» d6[7], r2
211 ; ASM-NEXT:» vmov.s8»r0, d1[0]
212 ; ASM-NEXT:» vmov.s8»r1, d3[0]
213 ; ASM-NEXT:» vmov.s8»r2, d5[0]
214 ; ASM-NEXT:» tst» r0, #1
215 ; ASM-NEXT:» movne» r2, r1
216 ; ASM-NEXT:» vmov.8» d7[0], r2
217 ; ASM-NEXT:» vmov.s8»r0, d1[1]
218 ; ASM-NEXT:» vmov.s8»r1, d3[1]
219 ; ASM-NEXT:» vmov.s8»r2, d5[1]
220 ; ASM-NEXT:» tst» r0, #1
221 ; ASM-NEXT:» movne» r2, r1
222 ; ASM-NEXT:» vmov.8» d7[1], r2
223 ; ASM-NEXT:» vmov.s8»r0, d1[2]
224 ; ASM-NEXT:» vmov.s8»r1, d3[2]
225 ; ASM-NEXT:» vmov.s8»r2, d5[2]
226 ; ASM-NEXT:» tst» r0, #1
227 ; ASM-NEXT:» movne» r2, r1
228 ; ASM-NEXT:» vmov.8» d7[2], r2
229 ; ASM-NEXT:» vmov.s8»r0, d1[3]
230 ; ASM-NEXT:» vmov.s8»r1, d3[3]
231 ; ASM-NEXT:» vmov.s8»r2, d5[3]
232 ; ASM-NEXT:» tst» r0, #1
233 ; ASM-NEXT:» movne» r2, r1
234 ; ASM-NEXT:» vmov.8» d7[3], r2
235 ; ASM-NEXT:» vmov.s8»r0, d1[4]
236 ; ASM-NEXT:» vmov.s8»r1, d3[4]
237 ; ASM-NEXT:» vmov.s8»r2, d5[4]
238 ; ASM-NEXT:» tst» r0, #1
239 ; ASM-NEXT:» movne» r2, r1
240 ; ASM-NEXT:» vmov.8» d7[4], r2
241 ; ASM-NEXT:» vmov.s8»r0, d1[5]
242 ; ASM-NEXT:» vmov.s8»r1, d3[5]
243 ; ASM-NEXT:» vmov.s8»r2, d5[5]
244 ; ASM-NEXT:» tst» r0, #1
245 ; ASM-NEXT:» movne» r2, r1
246 ; ASM-NEXT:» vmov.8» d7[5], r2
247 ; ASM-NEXT:» vmov.s8»r0, d1[6]
248 ; ASM-NEXT:» vmov.s8»r1, d3[6]
249 ; ASM-NEXT:» vmov.s8»r2, d5[6]
250 ; ASM-NEXT:» tst» r0, #1
251 ; ASM-NEXT:» movne» r2, r1
252 ; ASM-NEXT:» vmov.8» d7[6], r2
253 ; ASM-NEXT:» vmov.s8»r0, d1[7]
254 ; ASM-NEXT:» vmov.s8»r1, d3[7]
255 ; ASM-NEXT:» vmov.s8»r2, d5[7]
256 ; ASM-NEXT:» tst» r0, #1
257 ; ASM-NEXT:» movne» r2, r1
258 ; ASM-NEXT:» vmov.8» d7[7], r2
259 ; ASM-NEXT:» vmov.i8»q0, q3
260 ; ASM-NEXT:» bx» lr
261 104
262 ret <16 x i8> %res 105 ret <16 x i8> %res
263 } 106 }
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