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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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847 void _vabs(Variable *Dest, Variable *Src, | 847 void _vabs(Variable *Dest, Variable *Src, |
848 CondARM32::Cond Pred = CondARM32::AL) { | 848 CondARM32::Cond Pred = CondARM32::AL) { |
849 Context.insert<InstARM32Vabs>(Dest, Src, Pred); | 849 Context.insert<InstARM32Vabs>(Dest, Src, Pred); |
850 } | 850 } |
851 void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) { | 851 void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) { |
852 Context.insert<InstARM32Vadd>(Dest, Src0, Src1); | 852 Context.insert<InstARM32Vadd>(Dest, Src0, Src1); |
853 } | 853 } |
854 void _vand(Variable *Dest, Variable *Src0, Variable *Src1) { | 854 void _vand(Variable *Dest, Variable *Src0, Variable *Src1) { |
855 Context.insert<InstARM32Vand>(Dest, Src0, Src1); | 855 Context.insert<InstARM32Vand>(Dest, Src0, Src1); |
856 } | 856 } |
| 857 InstARM32Vbsl *_vbsl(Variable *Dest, Variable *Src0, Variable *Src1) { |
| 858 return Context.insert<InstARM32Vbsl>(Dest, Src0, Src1); |
| 859 } |
857 void _vcvt(Variable *Dest, Variable *Src, InstARM32Vcvt::VcvtVariant Variant, | 860 void _vcvt(Variable *Dest, Variable *Src, InstARM32Vcvt::VcvtVariant Variant, |
858 CondARM32::Cond Pred = CondARM32::AL) { | 861 CondARM32::Cond Pred = CondARM32::AL) { |
859 Context.insert<InstARM32Vcvt>(Dest, Src, Variant, Pred); | 862 Context.insert<InstARM32Vcvt>(Dest, Src, Variant, Pred); |
860 } | 863 } |
861 void _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) { | 864 void _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) { |
862 Context.insert<InstARM32Vdiv>(Dest, Src0, Src1); | 865 Context.insert<InstARM32Vdiv>(Dest, Src0, Src1); |
863 } | 866 } |
864 void _vcmp(Variable *Src0, Variable *Src1, | 867 void _vcmp(Variable *Src0, Variable *Src1, |
865 CondARM32::Cond Pred = CondARM32::AL) { | 868 CondARM32::Cond Pred = CondARM32::AL) { |
866 Context.insert<InstARM32Vcmp>(Src0, Src1, Pred); | 869 Context.insert<InstARM32Vcmp>(Src0, Src1, Pred); |
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1350 private: | 1353 private: |
1351 ~TargetHeaderARM32() = default; | 1354 ~TargetHeaderARM32() = default; |
1352 | 1355 |
1353 TargetARM32Features CPUFeatures; | 1356 TargetARM32Features CPUFeatures; |
1354 }; | 1357 }; |
1355 | 1358 |
1356 } // end of namespace ARM32 | 1359 } // end of namespace ARM32 |
1357 } // end of namespace Ice | 1360 } // end of namespace Ice |
1358 | 1361 |
1359 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 1362 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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