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| 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// | 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 854 scalarizeInstruction( | 854 scalarizeInstruction( |
| 855 Dest, | 855 Dest, |
| 856 [this, Condition](Variable *Dest, Variable *Src0, Variable *Src1) { | 856 [this, Condition](Variable *Dest, Variable *Src0, Variable *Src1) { |
| 857 return Context.insert<InstFcmp>(Condition, Dest, Src0, Src1); | 857 return Context.insert<InstFcmp>(Condition, Dest, Src0, Src1); |
| 858 }, | 858 }, |
| 859 CmpInstr->getSrc(0), CmpInstr->getSrc(1)); | 859 CmpInstr->getSrc(0), CmpInstr->getSrc(1)); |
| 860 CmpInstr->setDeleted(); | 860 CmpInstr->setDeleted(); |
| 861 } | 861 } |
| 862 return; | 862 return; |
| 863 } | 863 } |
| 864 case Inst::Select: { | |
| 865 Variable *Dest = Instr->getDest(); | |
| 866 const auto DestTy = Dest->getType(); | |
| 867 if (isVectorType(DestTy)) { | |
| 868 auto *SelectInstr = llvm::cast<InstSelect>(Instr); | |
| 869 scalarizeInstruction(Dest, | |
| 870 [this](Variable *Dest, Variable *Src0, | |
| 871 Variable *Src1, Variable *Src2) { | |
| 872 return Context.insert<InstSelect>(Dest, Src0, Src1, | |
| 873 Src2); | |
| 874 }, | |
| 875 llvm::cast<Variable>(SelectInstr->getSrc(0)), | |
| 876 llvm::cast<Variable>(SelectInstr->getSrc(1)), | |
| 877 llvm::cast<Variable>(SelectInstr->getSrc(2))); | |
| 878 SelectInstr->setDeleted(); | |
| 879 } | |
| 880 return; | |
| 881 } | |
| 882 } | 864 } |
| 883 } | 865 } |
| 884 | 866 |
| 885 void TargetARM32::findMaxStackOutArgsSize() { | 867 void TargetARM32::findMaxStackOutArgsSize() { |
| 886 // MinNeededOutArgsBytes should be updated if the Target ever creates a | 868 // MinNeededOutArgsBytes should be updated if the Target ever creates a |
| 887 // high-level InstCall that requires more stack bytes. | 869 // high-level InstCall that requires more stack bytes. |
| 888 constexpr size_t MinNeededOutArgsBytes = 0; | 870 constexpr size_t MinNeededOutArgsBytes = 0; |
| 889 MaxOutArgsSizeBytes = MinNeededOutArgsBytes; | 871 MaxOutArgsSizeBytes = MinNeededOutArgsBytes; |
| 890 for (CfgNode *Node : Func->getNodes()) { | 872 for (CfgNode *Node : Func->getNodes()) { |
| 891 Context.init(Node); | 873 Context.init(Node); |
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| 5720 Context.insert<InstFakeUse>(SP); | 5702 Context.insert<InstFakeUse>(SP); |
| 5721 } | 5703 } |
| 5722 | 5704 |
| 5723 void TargetARM32::lowerSelect(const InstSelect *Instr) { | 5705 void TargetARM32::lowerSelect(const InstSelect *Instr) { |
| 5724 Variable *Dest = Instr->getDest(); | 5706 Variable *Dest = Instr->getDest(); |
| 5725 Type DestTy = Dest->getType(); | 5707 Type DestTy = Dest->getType(); |
| 5726 Operand *SrcT = Instr->getTrueOperand(); | 5708 Operand *SrcT = Instr->getTrueOperand(); |
| 5727 Operand *SrcF = Instr->getFalseOperand(); | 5709 Operand *SrcF = Instr->getFalseOperand(); |
| 5728 Operand *Condition = Instr->getCondition(); | 5710 Operand *Condition = Instr->getCondition(); |
| 5729 | 5711 |
| 5730 if (isVectorType(DestTy)) { | 5712 if (!isVectorType(DestTy)) { |
| 5731 UnimplementedLoweringError(this, Instr); | 5713 lowerInt1ForSelect(Dest, Condition, legalizeUndef(SrcT), |
| 5714 legalizeUndef(SrcF)); |
| 5732 return; | 5715 return; |
| 5733 } | 5716 } |
| 5734 | 5717 |
| 5735 lowerInt1ForSelect(Dest, Condition, legalizeUndef(SrcT), legalizeUndef(SrcF)); | 5718 Type TType = DestTy; |
| 5719 switch (DestTy) { |
| 5720 default: |
| 5721 llvm::report_fatal_error("Unexpected type for vector select."); |
| 5722 case IceType_v4i1: |
| 5723 TType = IceType_v4i32; |
| 5724 break; |
| 5725 case IceType_v8i1: |
| 5726 TType = IceType_v8i16; |
| 5727 break; |
| 5728 case IceType_v16i1: |
| 5729 TType = IceType_v16i8; |
| 5730 break; |
| 5731 case IceType_v4f32: |
| 5732 TType = IceType_v4i32; |
| 5733 break; |
| 5734 case IceType_v4i32: |
| 5735 case IceType_v8i16: |
| 5736 case IceType_v16i8: |
| 5737 break; |
| 5738 } |
| 5739 auto *T = makeReg(TType); |
| 5740 lowerCast(InstCast::create(Func, InstCast::Sext, T, Condition)); |
| 5741 auto *SrcTR = legalizeToReg(SrcT); |
| 5742 auto *SrcFR = legalizeToReg(SrcF); |
| 5743 _vbsl(T, SrcTR, SrcFR)->setDestRedefined(); |
| 5744 _mov(Dest, T); |
| 5736 } | 5745 } |
| 5737 | 5746 |
| 5738 void TargetARM32::lowerStore(const InstStore *Instr) { | 5747 void TargetARM32::lowerStore(const InstStore *Instr) { |
| 5739 Operand *Value = Instr->getData(); | 5748 Operand *Value = Instr->getData(); |
| 5740 Operand *Addr = Instr->getAddr(); | 5749 Operand *Addr = Instr->getAddr(); |
| 5741 OperandARM32Mem *NewAddr = formMemoryOperand(Addr, Value->getType()); | 5750 OperandARM32Mem *NewAddr = formMemoryOperand(Addr, Value->getType()); |
| 5742 Type Ty = NewAddr->getType(); | 5751 Type Ty = NewAddr->getType(); |
| 5743 | 5752 |
| 5744 if (Ty == IceType_i64) { | 5753 if (Ty == IceType_i64) { |
| 5745 Value = legalizeUndef(Value); | 5754 Value = legalizeUndef(Value); |
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| 6985 // However, for compatibility with current NaCl LLVM, don't claim that. | 6994 // However, for compatibility with current NaCl LLVM, don't claim that. |
| 6986 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; | 6995 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; |
| 6987 } | 6996 } |
| 6988 | 6997 |
| 6989 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM]; | 6998 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM]; |
| 6990 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM]; | 6999 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM]; |
| 6991 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; | 7000 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; |
| 6992 | 7001 |
| 6993 } // end of namespace ARM32 | 7002 } // end of namespace ARM32 |
| 6994 } // end of namespace Ice | 7003 } // end of namespace Ice |
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