Subzero. ARM32. Implements vector select.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2392 matching lines @@
   // VAND (register) - ARM section A8.8.287, encoding A1:
   //   vand <Qd>, <Qn>, <Qm>
   //
   // 111100100D00nnn0ddd00001N1M1mmm0 where Dddd=OpQd, Nnnn=OpQm, and Mmmm=OpQm.
   constexpr const char *Vandq = "vandq";
   constexpr IValueT VandqOpcode = B8 | B4;
   constexpr Type ElmtTy = IceType_i8;
   emitSIMDqqq(VandqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vandq);
 }
 
+void AssemblerARM32::vbslq(const Operand *OpQd, const Operand *OpQm,
+                           const Operand *OpQn) {
+  // VBSL (register) - ARM section A8.8.290, encoding A1:
+  //   vbsl <Qd>, <Qn>, <Qm>
+  //
+  // 111100110D01nnn0ddd00001N1M1mmm0 where Dddd=OpQd, Nnnn=OpQm, and Mmmm=OpQm.
+  constexpr const char *Vbslq = "vbslq";
+  constexpr IValueT VbslqOpcode = B24 | B20 | B8 | B4;
+  constexpr Type ElmtTy = IceType_i8; // emits sz=0
+  emitSIMDqqq(VbslqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vbslq);
+}
+
 void AssemblerARM32::vcmpd(const Operand *OpDd, const Operand *OpDm,
                            CondARM32::Cond Cond) {
   constexpr const char *Vcmpd = "vcmpd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vcmpd);
   IValueT Dm = encodeDRegister(OpDm, "Dm", Vcmpd);
   constexpr IValueT VcmpdOpcode = B23 | B21 | B20 | B18 | B6;
   constexpr IValueT Dn = 0;
   emitVFPddd(Cond, VcmpdOpcode, Dd, Dn, Dm);
 }
 
@@ skipping 1020 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice