Subzero. ARM32. Implements vector select.

tests_lit/assembler/arm32/vec-sh-imm.ll

 ; Show that we know how to translate vshl and vshr with immediate shift amounts.
 ; We abuse sign extension of vectors of i1 because that's the only way to force
 ; Subzero to emit these instructions.
 
 ; NOTE: We use -O2 to get rid of memory stores.
 
 ; REQUIRES: allow_dump
 
 ; Compile using standalone assembler.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
@@ skipping 16 matching lines @@
 ; DIS-LABEL:00000000 <SextV4I1>:
 ; IASM-LABEL:SextV4I1:
 
   %trunc = trunc <4 x i32> %a to <4 x i1>
   %sext = sext <4 x i1> %trunc to <4 x i32>
   ret <4 x i32> %sext
 ; ASM:         vshl.u32 {{.*}}, #31
 ; ASM-NEXT:    vshr.s32 {{.*}}, #31
 ; DIS:      0: f2bf0550
 ; DIS-NEXT: 4: f2a10050
-; IASM-NOT:    vshl.u32 {{.*}}, #31
-; IASM-NOT:    vshr.s32 {{.*}}, #31
+; IASM-NOT:    vshl
+; IASM-NOT:    vshr
 }
 
 define internal <8 x i16> @SextV8I1(<8 x i16> %a) {
 ; ASM-LABEL:SextV8I1
 ; DIS-LABEL:00000010 <SextV8I1>:
 ; IASM-LABEL:SextV8I1:
 
   %trunc = trunc <8 x i16> %a to <8 x i1>
   %sext = sext <8 x i1> %trunc to <8 x i16>
   ret <8 x i16> %sext
-; ASM:      vshl.u16 {{.*}}, #15
-; ASM-NEXT: vshr.s16 {{.*}}, #15
+; ASM:          vshl.u16 {{.*}}, #15
+; ASM-NEXT:     vshr.s16 {{.*}}, #15
 ; DIS:      10: f29f0550
 ; DIS-NEXT: 14: f2910050
-; IASM-NOT: vshl.u16 {{.*}}, #15
-; IASM-NOT: vshr.s16 {{.*}}, #15
+; IASM-NOT:     vshl
+; IASM-NOT:     vshr
 }
 
 define internal <16 x i8> @SextV16I1(<16 x i8> %a) {
 ; ASM-LABEL:SextV16I1
 ; DIS-LABEL:00000020 <SextV16I1>:
 ; IASM-LABEL:SextV16I1:
 
   %trunc = trunc <16 x i8> %a to <16 x i1>
   %sext = sext <16 x i1> %trunc to <16 x i8>
   ret <16 x i8> %sext
-; ASM:      vshl.u8 {{.*}}, #7
-; ASM-NEXT: vshr.s8 {{.*}}, #7
+; ASM:          vshl.u8 {{.*}}, #7
+; ASM-NEXT:     vshr.s8 {{.*}}, #7
 ; DIS:      20: f28f0550
 ; DIS-NEXT: 24: f2890050
-; IASM-NOT: vshl.u8 {{.*}}, #7
-; IASM-NOT: vshr.s8 {{.*}}, #7
+; IASM-NOT:     vshl
+; IASM-NOT:     vshr
 }