[turbofan] ARM: elide masks on loads and stores

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/adapters.h"
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
@@ skipping 286 matching lines @@
   if (selector->IsSupported(MLS)) {
     selector->Emit(kArmMls, result_operand, div_operand, right_operand,
                    left_operand);
   } else {
     InstructionOperand mul_operand = g.TempRegister();
     selector->Emit(kArmMul, mul_operand, div_operand, right_operand);
     selector->Emit(kArmSub, result_operand, left_operand, mul_operand);
   }
 }
 
+void EmitLoad(InstructionSelector* selector, ArchOpcode opcode, Node* node,
+              Node* const base, Node* const index) {
+  ArmOperandGenerator g(selector);
+  InstructionCode icode;
+  InstructionOperand index_operand;
+  if (g.CanBeImmediate(index, opcode)) {
+    icode = opcode | AddressingModeField::encode(kMode_Offset_RI);
+    index_operand = g.UseImmediate(index);
+  } else {
+    icode = opcode | AddressingModeField::encode(kMode_Offset_RR);
+    index_operand = g.UseRegister(index);
+  }
+  selector->Emit(icode, g.DefineAsRegister(node), g.UseRegister(base),
+                 index_operand);
+}
+
+void EmitCheckedLoad(InstructionSelector* selector, ArchOpcode opcode,
+                     Node* node, Node* const buffer, Node* const offset,
+                     Node* const length) {
+  ArmOperandGenerator g(selector);
+  InstructionOperand offset_operand = g.UseRegister(offset);
+  InstructionOperand length_operand = g.CanBeImmediate(length, kArmCmp)
+                                          ? g.UseImmediate(length)
+                                          : g.UseRegister(length);
+  selector->Emit(opcode | AddressingModeField::encode(kMode_Offset_RR),
+                 g.DefineAsRegister(node), offset_operand, length_operand,
+                 g.UseRegister(buffer), offset_operand);
+}
+
+// Simplify or elide mask on 8-bit and 16-bit stores. Returns the input node of
+// the mask operation if it can be elided, otherwise the value node.
+Node* SimplifyAndForMaskedStore(InstructionSelector* selector, Node* node,

[Benedikt Meurer, 2016/04/14 18:39:58]

This looks like something that should be done in the MachineOperatorReducer, as
it applies to all platforms. Can you move it there instead?

[martyn.capewell, 2016/04/15 14:05:49]

You're right, I should update MachineOperatorReducer::ReduceStore() for elision
on Checked operations.

However, the simplification part is machine specific. For example, on ARM64, the
immediate 0xfffffffd is encodable in the instruction, but the simplified
immediates 0xfffd or 0xfd aren't. ARM64 would then need a "complexify" operation
to make 0xfffd into 0xfffdfffd, which is encodable.

+                                Node* value, ArchOpcode opcode) {
+  ArmOperandGenerator g(selector);
+  NodeMatcher nm(value);
+  if (nm.IsWord32And() && selector->CanCover(node, value)) {
+    Uint32BinopMatcher m(value);
+    if (m.right().HasValue()) {
+      uint32_t mask = m.right().Value();
+
+      // Rewrite the opcode to make the later if statement simpler.
+      opcode = (opcode == kCheckedStoreWord8) ? kArmStrb : opcode;
+      opcode = (opcode == kCheckedStoreWord16) ? kArmStrh : opcode;
+
+      if (((opcode == kArmStrb) && ((mask & 0xff) == 0xff)) ||
+          ((opcode == kArmStrh) && ((mask & 0xffff) == 0xffff))) {
+        // The masking operation can be elided, so return the left input to the
+        // mask.
+        return m.left().node();
+      } else if (opcode == kArmStrh) {
+        // Strh effectively applies a mask of 0xffff, so simplify the AND's mask
+        // using this, with the aim of making the new immediate encodable in the
+        // instruction.
+        mask &= 0xffff;
+        if (g.CanBeImmediate(mask)) {
+          selector->Emit(
+              kArmAnd | AddressingModeField::encode(kMode_Operand2_I),
+              g.DefineAsRegister(value), g.UseRegister(m.left().node()),
+              g.TempImmediate(mask));
+        } else if (g.CanBeImmediate(mask ^ 0xffff)) {
+          selector->Emit(
+              kArmBic | AddressingModeField::encode(kMode_Operand2_I),
+              g.DefineAsRegister(value), g.UseRegister(m.left().node()),
+              g.TempImmediate(mask ^ 0xffff));
+        }
+      }
+      // TODO(turbofan): Consider similar optimisation for strb/and 0xff.
+    }
+  }
+  return value;
+}
+
 }  // namespace
 
 
 void InstructionSelector::VisitLoad(Node* node) {
   LoadRepresentation load_rep = LoadRepresentationOf(node->op());
   ArmOperandGenerator g(this);
   Node* base = node->InputAt(0);
   Node* index = node->InputAt(1);
 
   ArchOpcode opcode = kArchNop;
@@ skipping 15 matching lines @@
     case MachineRepresentation::kWord32:
       opcode = kArmLdr;
       break;
     case MachineRepresentation::kWord64:   // Fall through.
     case MachineRepresentation::kSimd128:  // Fall through.
     case MachineRepresentation::kNone:
       UNREACHABLE();
       return;
   }
 
-  if (g.CanBeImmediate(index, opcode)) {
-    Emit(opcode | AddressingModeField::encode(kMode_Offset_RI),
-         g.DefineAsRegister(node), g.UseRegister(base), g.UseImmediate(index));
-  } else {
-    Emit(opcode | AddressingModeField::encode(kMode_Offset_RR),
-         g.DefineAsRegister(node), g.UseRegister(base), g.UseRegister(index));
-  }
+  EmitLoad(this, opcode, node, base, index);
 }
 
 
 void InstructionSelector::VisitStore(Node* node) {
   ArmOperandGenerator g(this);
   Node* base = node->InputAt(0);
   Node* index = node->InputAt(1);
   Node* value = node->InputAt(2);
 
   StoreRepresentation store_rep = StoreRepresentationOf(node->op());
@@ skipping 57 matching lines @@
       case MachineRepresentation::kWord32:
         opcode = kArmStr;
         break;
       case MachineRepresentation::kWord64:   // Fall through.
       case MachineRepresentation::kSimd128:  // Fall through.
       case MachineRepresentation::kNone:
         UNREACHABLE();
         return;
     }
 
+    value = SimplifyAndForMaskedStore(this, node, value, opcode);
+
     if (g.CanBeImmediate(index, opcode)) {
       Emit(opcode | AddressingModeField::encode(kMode_Offset_RI), g.NoOutput(),
            g.UseRegister(base), g.UseImmediate(index), g.UseRegister(value));
     } else {
       Emit(opcode | AddressingModeField::encode(kMode_Offset_RR), g.NoOutput(),
            g.UseRegister(base), g.UseRegister(index), g.UseRegister(value));
     }
   }
 }
 
@@ skipping 22 matching lines @@
       opcode = kCheckedLoadFloat64;
       break;
     case MachineRepresentation::kBit:      // Fall through.
     case MachineRepresentation::kTagged:   // Fall through.
     case MachineRepresentation::kWord64:   // Fall through.
     case MachineRepresentation::kSimd128:  // Fall through.
     case MachineRepresentation::kNone:
       UNREACHABLE();
       return;
   }
-  InstructionOperand offset_operand = g.UseRegister(offset);
-  InstructionOperand length_operand = g.CanBeImmediate(length, kArmCmp)
-                                          ? g.UseImmediate(length)
-                                          : g.UseRegister(length);
-  Emit(opcode | AddressingModeField::encode(kMode_Offset_RR),
-       g.DefineAsRegister(node), offset_operand, length_operand,
-       g.UseRegister(buffer), offset_operand);
+  EmitCheckedLoad(this, opcode, node, buffer, offset, length);
 }
 
 
 void InstructionSelector::VisitCheckedStore(Node* node) {
   MachineRepresentation rep = CheckedStoreRepresentationOf(node->op());
   ArmOperandGenerator g(this);
   Node* const buffer = node->InputAt(0);
   Node* const offset = node->InputAt(1);
   Node* const length = node->InputAt(2);
-  Node* const value = node->InputAt(3);
+  Node* value = node->InputAt(3);
   ArchOpcode opcode = kArchNop;
   switch (rep) {
     case MachineRepresentation::kWord8:
       opcode = kCheckedStoreWord8;
       break;
     case MachineRepresentation::kWord16:
       opcode = kCheckedStoreWord16;
       break;
     case MachineRepresentation::kWord32:
       opcode = kCheckedStoreWord32;
       break;
     case MachineRepresentation::kFloat32:
       opcode = kCheckedStoreFloat32;
       break;
     case MachineRepresentation::kFloat64:
       opcode = kCheckedStoreFloat64;
       break;
     case MachineRepresentation::kBit:      // Fall through.
     case MachineRepresentation::kTagged:   // Fall through.
     case MachineRepresentation::kWord64:   // Fall through.
     case MachineRepresentation::kSimd128:  // Fall through.
     case MachineRepresentation::kNone:
       UNREACHABLE();
       return;
   }
+
+  value = SimplifyAndForMaskedStore(this, node, value, opcode);
+
   InstructionOperand offset_operand = g.UseRegister(offset);
   InstructionOperand length_operand = g.CanBeImmediate(length, kArmCmp)
                                           ? g.UseImmediate(length)
                                           : g.UseRegister(length);
   Emit(opcode | AddressingModeField::encode(kMode_Offset_RR), g.NoOutput(),
        offset_operand, length_operand, g.UseRegister(value),
        g.UseRegister(buffer), offset_operand);
 }
 
 
@@ skipping 18 matching lines @@
 
 void EmitUbfx(InstructionSelector* selector, Node* node, Node* left,
               uint32_t lsb, uint32_t width) {
   DCHECK_LE(1u, width);
   DCHECK_LE(width, 32u - lsb);
   ArmOperandGenerator g(selector);
   selector->Emit(kArmUbfx, g.DefineAsRegister(node), g.UseRegister(left),
                  g.TempImmediate(lsb), g.TempImmediate(width));
 }
 
+// Try to emit an AND or BIC instruction when the left input is an 8/16-bit
+// load. Returns true if an instruction was emitted, false otherwise.
+bool TryEmitAndForMaskedLoad(InstructionSelector* selector, Node* node,
+                             MachineType type, uint32_t value) {
+  ArmOperandGenerator g(selector);
+  Int32BinopMatcher m(node);
+  if (type == MachineType::Uint16()) {
+    // The input load has already applied a 0xffff mask to the input, so
+    // simplify the value and test if it's an immediate that can be encoded in
+    // the instruction.
+    value &= 0xffff;
+    if (g.CanBeImmediate(value)) {
+      selector->Emit(kArmAnd | AddressingModeField::encode(kMode_Operand2_I),
+                     g.DefineAsRegister(node), g.UseRegister(m.left().node()),
+                     g.TempImmediate(value));
+      return true;
+    }
+    // Test if an inverted value can be used with BIC.
+    if (g.CanBeImmediate(value ^ 0xffff)) {
+      selector->Emit(kArmBic | AddressingModeField::encode(kMode_Operand2_I),
+                     g.DefineAsRegister(node), g.UseRegister(m.left().node()),
+                     g.TempImmediate(value ^ 0xffff));
+      return true;
+    }
+  } else if (type == MachineType::Uint8()) {
+    // The input load has already applied a 0xff mask to the input.
+    value &= 0xff;
+    DCHECK(g.CanBeImmediate(value));  // All 8-bit values are encodable.
+    selector->Emit(kArmAnd | AddressingModeField::encode(kMode_Operand2_I),
+                   g.DefineAsRegister(node), g.UseRegister(m.left().node()),
+                   g.TempImmediate(value));
+    return true;
+  }
+  return false;
+}
+
 }  // namespace
 
 
 void InstructionSelector::VisitWord32And(Node* node) {
   ArmOperandGenerator g(this);
   Int32BinopMatcher m(node);
   if (m.left().IsWord32Xor() && CanCover(node, m.left().node())) {
     Int32BinopMatcher mleft(m.left().node());
     if (mleft.right().Is(-1)) {
       EmitBic(this, node, m.right().node(), mleft.left().node());
       return;
     }
   }
   if (m.right().IsWord32Xor() && CanCover(node, m.right().node())) {
     Int32BinopMatcher mright(m.right().node());
     if (mright.right().Is(-1)) {
       EmitBic(this, node, m.left().node(), mright.left().node());
       return;
     }
   }
   if (m.right().HasValue()) {
     uint32_t const value = m.right().Value();
     uint32_t width = base::bits::CountPopulation32(value);
     uint32_t leading_zeros = base::bits::CountLeadingZeros32(value);
 
+    if (m.left().IsLoad()) {
+      LoadRepresentation load_rep = LoadRepresentationOf(m.left().node()->op());
+      if (CanCover(node, m.left().node()) &&
+          ((value == 0xff) || (value == 0xffff))) {
+        // Elide mask operation on load inputs by modifying the size of the
+        // load.
+        ArchOpcode opcode = kArmLdrb;
+        if ((value == 0xffff) &&
+            (load_rep.representation() != MachineRepresentation::kWord8)) {
+          opcode = kArmLdrh;
+        }
+        EmitLoad(this, opcode, node, m.left().InputAt(0), m.left().InputAt(1));
+        return;
+      }
+      if (!g.CanBeImmediate(value) &&
+          TryEmitAndForMaskedLoad(this, node, load_rep, value)) {
+        return;
+      }
+    } else if (m.left().IsCheckedLoad()) {
+      CheckedLoadRepresentation load_rep =
+          CheckedLoadRepresentationOf(m.left().node()->op());
+      if (CanCover(node, m.left().node()) &&
+          ((value == 0xff) || (value == 0xffff))) {
+        // Elide mask operation on load inputs by modifying the size of the
+        // load.
+        ArchOpcode opcode = kCheckedLoadUint8;
+        if ((value == 0xffff) &&
+            (load_rep.representation() != MachineRepresentation::kWord8)) {
+          opcode = kCheckedLoadUint16;
+        }
+        EmitCheckedLoad(this, opcode, node, m.left().InputAt(0),
+                        m.left().InputAt(1), m.left().InputAt(2));
+        return;
+      }
+      if (!g.CanBeImmediate(value) &&
+          TryEmitAndForMaskedLoad(this, node, load_rep, value)) {
+        return;
+      }
+    }
+
     // Try to merge SHR operations on the left hand input into this AND.
     if (m.left().IsWord32Shr()) {
       Int32BinopMatcher mshr(m.left().node());
       if (mshr.right().HasValue()) {
         uint32_t const shift = mshr.right().Value();
 
         if (((shift == 8) || (shift == 16) || (shift == 24)) &&
             ((value == 0xff) || (value == 0xffff))) {
           // Merge SHR into AND by emitting a UXTB or UXTH instruction with a
           // bytewise rotation.
@@ skipping 1255 matching lines @@
              MachineOperatorBuilder::kFloat32Max |
              MachineOperatorBuilder::kFloat64Min |
              MachineOperatorBuilder::kFloat64Max;
   }
   return flags;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8