Subzero. ARM32. Vector shifts.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 436 matching lines @@
     return;
   case Inst::Arithmetic: {
     Variable *Dest = Instr->getDest();
     const Type DestTy = Dest->getType();
     const InstArithmetic::OpKind Op =
         llvm::cast<InstArithmetic>(Instr)->getOp();
     if (isVectorType(DestTy)) {
       switch (Op) {
       default:
         break;
-      case InstArithmetic::Ashr:
       case InstArithmetic::Fdiv:
       case InstArithmetic::Frem:
-      case InstArithmetic::Lshr:
       case InstArithmetic::Sdiv:
-      case InstArithmetic::Shl:
       case InstArithmetic::Srem:
       case InstArithmetic::Udiv:
       case InstArithmetic::Urem:
         scalarizeArithmetic(Op, Dest, Instr->getSrc(0), Instr->getSrc(1));
         Instr->setDeleted();
         return;
       }
     }
     switch (DestTy) {
     default:
@@ skipping 1480 matching lines @@
 
 // ARM32 address modes:
 //  ld/st i[8|16|32]: [reg], [reg +/- imm12], [pc +/- imm12],
 //                    [reg +/- reg << shamt5]
 //  ld/st f[32|64]  : [reg], [reg +/- imm8] , [pc +/- imm8]
 //  ld/st vectors   : [reg]
 //
 // For now, we don't handle address modes with Relocatables.
 namespace {
 // MemTraits contains per-type valid address mode information.
-#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr, shaddr)  \
+#define X(tag, elementty, int_width, fp_width, uvec_width, svec_width, sbits,  \
+          ubits, rraddr, shaddr)                                               \
   static_assert(!(shaddr) || rraddr, "Check ICETYPEARM32_TABLE::" #tag);
 ICETYPEARM32_TABLE
 #undef X
 
 static const struct {
   int32_t ValidImmMask;
   bool CanHaveImm;
   bool CanHaveIndex;
   bool CanHaveShiftedIndex;
 } MemTraits[] = {
-#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr, shaddr)  \
+#define X(tag, elementty, int_width, fp_width, uvec_width, svec_width, sbits,  \
+          ubits, rraddr, shaddr)                                               \
   { (1 << ubits) - 1, (ubits) > 0, rraddr, shaddr, }                           \
   ,
     ICETYPEARM32_TABLE
 #undef X
 };
 static constexpr SizeT MemTraitsSize = llvm::array_lengthof(MemTraits);
 } // end of anonymous namespace
 
 OperandARM32Mem *
 TargetARM32::PostLoweringLegalizer::legalizeMemOperand(OperandARM32Mem *Mem,
@@ skipping 1128 matching lines @@
     lowerInt64Arithmetic(Instr->getOp(), Instr->getDest(), Src0, Src1);
     return;
   }
 
   if (isVectorType(DestTy)) {
     switch (Instr->getOp()) {
     default:
       UnimplementedLoweringError(this, Instr);
       return;
     // Explicitly whitelist vector instructions we have implemented/enabled.
+    case InstArithmetic::Add:
+    case InstArithmetic::And:
+    case InstArithmetic::Ashr:
     case InstArithmetic::Fadd:
-    case InstArithmetic::Add:
+    case InstArithmetic::Fmul:
     case InstArithmetic::Fsub:
+    case InstArithmetic::Lshr:
+    case InstArithmetic::Mul:
+    case InstArithmetic::Or:
+    case InstArithmetic::Shl:
     case InstArithmetic::Sub:
-    case InstArithmetic::And:
-    case InstArithmetic::Or:
     case InstArithmetic::Xor:
-    case InstArithmetic::Fmul:
-    case InstArithmetic::Mul:
       break;
     }
   }
 
   Variable *T = makeReg(DestTy);
 
   // * Handle div/rem separately. They require a non-legalized Src1 to inspect
   // whether or not Src1 is a non-zero constant. Once legalized it is more
   // difficult to determine (constant may be moved to a register).
   // * Handle floating point arithmetic separately: they require Src1 to be
@@ skipping 299 matching lines @@
     if (isVectorType(DestTy)) {
       _vmul(T, Src0R, Src1R);
     } else {
       _mul(T, Src0R, Src1R);
     }
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Shl: {
     Variable *Src0R = Srcs.unswappedSrc0R(this);
-    Operand *Src1R = Srcs.unswappedSrc1RShAmtImm(this);
-    _lsl(T, Src0R, Src1R);
+    if (!isVectorType(T->getType())) {
+      Operand *Src1R = Srcs.unswappedSrc1RShAmtImm(this);
+      _lsl(T, Src0R, Src1R);
+    } else {
+      auto *Src1R = Srcs.unswappedSrc1R(this);
+      _vshl(T, Src0R, Src1R)->setSignType(InstARM32::FS_Unsigned);
+    }
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Lshr: {
     Variable *Src0R = Srcs.unswappedSrc0R(this);
-    if (DestTy != IceType_i32) {
-      _uxt(Src0R, Src0R);
+    if (!isVectorType(T->getType())) {
+      Operand *Src1R = Srcs.unswappedSrc1RShAmtImm(this);
+      if (DestTy != IceType_i32) {
+        _uxt(Src0R, Src0R);
+      }
+      _lsr(T, Src0R, Src1R);
+    } else {
+      auto *Src1R = Srcs.unswappedSrc1R(this);
+      auto *Src1RNeg = makeReg(Src1R->getType());
+      _vneg(Src1RNeg, Src1R);
+      _vshl(T, Src0R, Src1RNeg)->setSignType(InstARM32::FS_Unsigned);
     }
-    _lsr(T, Src0R, Srcs.unswappedSrc1RShAmtImm(this));
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Ashr: {
     Variable *Src0R = Srcs.unswappedSrc0R(this);
-    if (DestTy != IceType_i32) {
-      _sxt(Src0R, Src0R);
+    if (!isVectorType(T->getType())) {
+      if (DestTy != IceType_i32) {
+        _sxt(Src0R, Src0R);
+      }
+      _asr(T, Src0R, Srcs.unswappedSrc1RShAmtImm(this));
+    } else {
+      auto *Src1R = Srcs.unswappedSrc1R(this);
+      auto *Src1RNeg = makeReg(Src1R->getType());
+      _vneg(Src1RNeg, Src1R);
+      _vshl(T, Src0R, Src1RNeg)->setSignType(InstARM32::FS_Signed);
     }
-    _asr(T, Src0R, Srcs.unswappedSrc1RShAmtImm(this));
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Udiv:
   case InstArithmetic::Sdiv:
   case InstArithmetic::Urem:
   case InstArithmetic::Srem:
     llvm::report_fatal_error(
         "Integer div/rem should have been handled earlier.");
     return;
@@ skipping 3431 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice