Subzero. ARM32. Vector shifts.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 473 matching lines @@
   // Integer vector multiply.
   void vmulqi(Type ElmtTy, const Operand *OpQd, const Operand *OpQn,
               const Operand *OpQm);
 
   // Float vector multiply.
   void vmulqf(const Operand *OpQd, const Operand *OpQn, const Operand *OpQm);
 
   void vmuls(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
              CondARM32::Cond Cond);
 
+  void vnegqs(Type ElmtTy, const Operand *OpQd, const Operand *OpQm);
+
   void vorrq(const Operand *OpQd, const Operand *OpQm, const Operand *OpQn);
 
   void vpop(const Variable *OpBaseReg, SizeT NumConsecRegs,
             CondARM32::Cond Cond);
 
   void vpush(const Variable *OpBaseReg, SizeT NumConsecRegs,
              CondARM32::Cond Cond);
 
+  void vshlqi(Type ElmtTy, const Operand *OpQd, const Operand *OpQm,
+              const Operand *OpQn);
+
+  void vshlqu(Type ElmtTy, const Operand *OpQd, const Operand *OpQm,
+              const Operand *OpQn);
+
   void vsqrtd(const Operand *OpDd, const Operand *OpDm, CondARM32::Cond Cond);
 
   void vsqrts(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond);
 
   void vstrd(const Operand *OpDd, const Operand *OpAddress,
              CondARM32::Cond Cond, const TargetInfo &TInfo);
 
   void vstrd(const Operand *OpDd, const Operand *OpAddress,
              CondARM32::Cond Cond, const TargetLowering *Lowering) {
     const TargetInfo TInfo(Lowering);
@@ skipping 246 matching lines @@
 
   void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd,
                   const Operand *OpSn, const Operand *OpSm,
                   const char *InstName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H