Subzero. ARM32. Vector shifts.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2986 matching lines @@
   //   vmul.f32 <Qd>, <Qn>, <Qm>
   //
   // 111100110D00nnn0ddd01101MqM1mmm0 where Dddd=Qd, Nnnn=Qn, and Mmmm=Qm.
   assert(OpQd->getType() == IceType_v4f32 && "vmulqf expects type <4 x float>");
   constexpr const char *Vmulqf = "vmulqf";
   constexpr IValueT VmulqfOpcode = B24 | B11 | B8 | B4;
   constexpr bool IsFloatTy = true;
   emitSIMDqqqBase(VmulqfOpcode, OpQd, OpQn, OpQm, IsFloatTy, Vmulqf);
 }
 
+void AssemblerARM32::vnegqs(Type ElmtTy, const Operand *OpQd,
+                            const Operand *OpQm) {
+  // VNEG - ARM section A8.8.355, encoding A1:
+  //   vneg.<dt> <Qd>, <Qm>
+  //
+  // 111111111D11ss01dddd0F111QM0mmmm where Dddd=Qd, and Mmmm=Qm, and:
+  //     * dt=s8  -> 00=ss, 0=F
+  //     * dt=s16 -> 01=ss, 0=F
+  //     * dt=s32 -> 10=ss, 0=F
+  //     * dt=s32 -> 10=ss, 1=F
+  constexpr const char *Vneg = "vneg";
+  constexpr IValueT VnegOpcode = B24 | B23 | B21 | B20 | B16 | B9 | B8 | B7;
+  const IValueT Qd = encodeQRegister(OpQd, "Qd", Vneg);
+  constexpr IValueT Qn = 0;
+  const IValueT Qm = encodeQRegister(OpQm, "Qm", Vneg);
+  constexpr bool UseQRegs = true;
+  constexpr IValueT ElmtShift = 18;
+  const IValueT ElmtSize = encodeElmtType(ElmtTy);
+  assert(Utils::IsUint(2, ElmtSize));
+  emitSIMDBase(VnegOpcode | (ElmtSize << ElmtShift), mapQRegToDReg(Qd),
+               mapQRegToDReg(Qn), mapQRegToDReg(Qm), UseQRegs,
+               isFloatingType(ElmtTy));
+}
+
 void AssemblerARM32::vorrq(const Operand *OpQd, const Operand *OpQm,
                            const Operand *OpQn) {
   // VORR (register) - ARM section A8.8.360, encoding A1:
   //   vorr <Qd>, <Qn>, <Qm>
   //
   // 111100100D10nnn0ddd00001N1M1mmm0 where Dddd=OpQd, Nnnn=OpQm, and Mmmm=OpQm.
   constexpr const char *Vorrq = "vorrq";
   constexpr IValueT VorrqOpcode = B21 | B8 | B4;
   constexpr Type ElmtTy = IceType_i8;
   emitSIMDqqq(VorrqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vorrq);
@@ skipping 153 matching lines @@
   // VPUSH - ARM section A8.8.368, encoding A2:
   //   vpush<c> <RegList>
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
+void AssemblerARM32::vshlqi(Type ElmtTy, const Operand *OpQd,
+                            const Operand *OpQm, const Operand *OpQn) {
+  // VSHL - ARM section A8.8.396, encoding A1:
+  //   vshl Qd, Qm, Qn
+  //
+  // 1111001U0Dssnnnndddd0100NQM0mmmm where Ddddd=Qd, Mmmmm=Qm, Nnnnn=Qn, 0=U,
+  // 1=Q
+  assert(isScalarIntegerType(ElmtTy) &&
+         "vshl expects vector with integer element type");
+  constexpr const char *Vshl = "vshl";
+  constexpr IValueT VshlOpcode = B10 | B6;
+  emitSIMDqqq(VshlOpcode, ElmtTy, OpQd, OpQn, OpQm, Vshl);
+}
+
+void AssemblerARM32::vshlqu(Type ElmtTy, const Operand *OpQd,
+                            const Operand *OpQm, const Operand *OpQn) {
+  // VSHL - ARM section A8.8.396, encoding A1:
+  //   vshl Qd, Qm, Qn
+  //
+  // 1111001U0Dssnnnndddd0100NQM0mmmm where Ddddd=Qd, Mmmmm=Qm, Nnnnn=Qn, 1=U,
+  // 1=Q
+  assert(isScalarIntegerType(ElmtTy) &&
+         "vshl expects vector with integer element type");
+  constexpr const char *Vshl = "vshl";
+  constexpr IValueT VshlOpcode = B24 | B10 | B6;
+  emitSIMDqqq(VshlOpcode, ElmtTy, OpQd, OpQn, OpQm, Vshl);
+}
+
 void AssemblerARM32::vsqrtd(const Operand *OpDd, const Operand *OpDm,
                             CondARM32::Cond Cond) {
   // VSQRT - ARM section A8.8.401, encoding A1:
   //   vsqrt<c>.f64 <Dd>, <Dm>
   //
   // cccc11101D110001dddd101111M0mmmm where cccc=Cond, Ddddd=Sd, and Mmmmm=Sm.
   constexpr const char *Vsqrtd = "vsqrtd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vsqrtd);
   IValueT Dm = encodeDRegister(OpDm, "Dm", Vsqrtd);
   constexpr IValueT VsqrtdOpcode = B23 | B21 | B20 | B16 | B7 | B6;
@@ skipping 10 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice