Chromium Code Reviews Chromium Code Reviews
Issue 1881623002:
Subzero. ARM32. Vector shifts. (Closed)
Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master| OLD | NEW |
|---|---|
| 1 ; Show that we know how to translate lsl. | 1 ; Show that we know how to translate lsl. |
| 2 | 2 |
| 3 ; NOTE: We use -O2 to get rid of memory stores. | 3 ; NOTE: We use -O2 to get rid of memory stores. |
| 4 | 4 |
| 5 ; REQUIRES: allow_dump | 5 ; REQUIRES: allow_dump |
| 6 | 6 |
| 7 ; Compile using standalone assembler. | 7 ; Compile using standalone assembler. |
| 8 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ | 8 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ |
| 9 ; RUN: | FileCheck %s --check-prefix=ASM | 9 ; RUN: | FileCheck %s --check-prefix=ASM |
| 10 | 10 |
| (...skipping 55 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 66 ; ASM-LABEL:ShlVec: | 66 ; ASM-LABEL:ShlVec: |
| 67 ; DIS-LABEL:00000020 <ShlVec>: | 67 ; DIS-LABEL:00000020 <ShlVec>: |
| 68 ; IASM-LABEL:ShlVec: | 68 ; IASM-LABEL:ShlVec: |
| 69 | 69 |
| 70 entry: | 70 entry: |
| 71 ; ASM-NEXT:.LShlVec$entry: | 71 ; ASM-NEXT:.LShlVec$entry: |
| 72 ; IASM-NEXT:.LShlVec$entry: | 72 ; IASM-NEXT:.LShlVec$entry: |
| 73 | 73 |
| 74 %shl = shl <4 x i32> %a, %b | 74 %shl = shl <4 x i32> %a, %b |
| 75 | 75 |
| 76 ; ASM: lsl r0, r0, r1 | 76 ; ASM: vshl.u32 q0, q0, q1 |
| 77 ; ASM: lsl r0, r0, r1 | 77 ; DIS: 20: f3220440 |
| 78 ; ASM: lsl r0, r0, r1 | 78 ; IASM: .byte 0x40 |
|
Karl
2016/04/13 16:17:37
Same here.
John
2016/04/15 13:20:57
Done.
| |
| 79 ; ASM: lsl r0, r0, r1 | 79 ; IASM-NEXT: .byte 0x4 |
| 80 ; DIS: 28: e1a00110 | 80 ; IASM-NEXT: .byte 0x22 |
| 81 ; IASM-NEXT: .byte 0xf3 | |
| 81 | 82 |
| 82 ret <4 x i32> %shl | 83 ret <4 x i32> %shl |
| 83 } | 84 } |
| 84 | 85 |
| 85 define internal <8 x i16> @ShlVeci16(<8 x i16> %a, <8 x i16> %b) { | 86 define internal <8 x i16> @ShlVeci16(<8 x i16> %a, <8 x i16> %b) { |
| 86 ; ASM-LABEL:ShlVeci16: | 87 ; ASM-LABEL:ShlVeci16: |
| 87 | 88 |
| 88 entry: | 89 entry: |
| 89 | 90 |
| 90 %v = shl <8 x i16> %a, %b | 91 %v = shl <8 x i16> %a, %b |
| 91 | 92 |
| 92 ; ASM: lsl r0, r0, r1 | 93 ; ASM: vshl.u16 q0, q0, q1 |
| 93 ; ASM: lsl r0, r0, r1 | 94 ; DIS: 30: f3120440 |
| 94 ; ASM: lsl r0, r0, r1 | 95 ; IASM: .byte 0x40 |
|
Karl
2016/04/13 16:17:37
Same here.
John
2016/04/15 13:20:57
Done.
| |
| 95 ; ASM: lsl r0, r0, r1 | 96 ; IASM-NEXT: .byte 0x4 |
| 96 ; ASM: lsl r0, r0, r1 | 97 ; IASM-NEXT: .byte 0x12 |
| 97 ; ASM: lsl r0, r0, r1 | 98 ; IASM-NEXT: .byte 0xf3 |
| 98 ; ASM: lsl r0, r0, r1 | |
| 99 ; ASM: lsl r0, r0, r1 | |
| 100 | 99 |
| 101 ret <8 x i16> %v | 100 ret <8 x i16> %v |
| 102 } | 101 } |
| 103 | 102 |
| 104 define internal <16 x i8> @ShlVeci8(<16 x i8> %a, <16 x i8> %b) { | 103 define internal <16 x i8> @ShlVeci8(<16 x i8> %a, <16 x i8> %b) { |
| 105 ; ASM-LABEL:ShlVeci8: | 104 ; ASM-LABEL:ShlVeci8: |
| 106 | 105 |
| 107 entry: | 106 entry: |
| 108 | 107 |
| 109 %v = shl <16 x i8> %a, %b | 108 %v = shl <16 x i8> %a, %b |
| 110 | 109 |
| 111 ; ASM: lsl r0, r0, r1 | 110 ; ASM: vshl.u8 q0, q0, q1 |
| 112 ; ASM: lsl r0, r0, r1 | 111 ; DIS: 40: f3020440 |
| 113 ; ASM: lsl r0, r0, r1 | 112 ; IASM: .byte 0x40 |
|
Karl
2016/04/13 16:17:37
Same here.
John
2016/04/15 13:20:57
Done.
| |
| 114 ; ASM: lsl r0, r0, r1 | 113 ; IASM-NEXT: .byte 0x4 |
| 115 ; ASM: lsl r0, r0, r1 | 114 ; IASM-NEXT: .byte 0x2 |
| 116 ; ASM: lsl r0, r0, r1 | 115 ; IASM-NEXT: .byte 0xf3 |
| 117 ; ASM: lsl r0, r0, r1 | |
| 118 ; ASM: lsl r0, r0, r1 | |
| 119 ; ASM: lsl r0, r0, r1 | |
| 120 ; ASM: lsl r0, r0, r1 | |
| 121 ; ASM: lsl r0, r0, r1 | |
| 122 ; ASM: lsl r0, r0, r1 | |
| 123 ; ASM: lsl r0, r0, r1 | |
| 124 ; ASM: lsl r0, r0, r1 | |
| 125 ; ASM: lsl r0, r0, r1 | |
| 126 ; ASM: lsl r0, r0, r1 | |
| 127 | 116 |
| 128 ret <16 x i8> %v | 117 ret <16 x i8> %v |
| 129 } | 118 } |
| OLD | NEW |
