Subzero. ARM32. Vector shifts.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 15 matching lines @@
 namespace ARM32 {
 
 namespace {
 
 using Register = RegARM32::AllRegisters;
 
 // maximum number of registers allowed in vpush/vpop.
 static constexpr SizeT VpushVpopMaxConsecRegs = 16;
 
 const struct TypeARM32Attributes_ {
-  const char *WidthString;    // b, h, <blank>, or d
-  const char *VecWidthString; // i8, i16, i32, f32, f64
+  const char *WidthString;     // b, h, <blank>, or d
+  const char *FpWidthString;   // i8, i16, i32, f32, f64
+  const char *SVecWidthString; // s8, s16, s32, f32
+  const char *UVecWidthString; // u8, u16, u32, f32
   int8_t SExtAddrOffsetBits;
   int8_t ZExtAddrOffsetBits;
 } TypeARM32Attributes[] = {
-#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr, shaddr)  \
-  { int_width, vec_width, sbits, ubits }                                       \
+#define X(tag, elementty, int_width, fp_width, uvec_width, svec_width, sbits,  \
+          ubits, rraddr, shaddr)                                               \
+  { int_width, fp_width, svec_width, uvec_width, sbits, ubits }                \
   ,
     ICETYPEARM32_TABLE
 #undef X
 };
 
 const struct InstARM32ShiftAttributes_ {
   const char *EmitString;
 } InstARM32ShiftAttributes[] = {
 #define X(tag, emit)                                                           \
   { emit }                                                                     \
@@ skipping 10 matching lines @@
   { CondARM32::opp, emit }                                                     \
   ,
     ICEINSTARM32COND_TABLE
 #undef X
 };
 
 size_t getVecElmtBitsize(Type Ty) {
   return typeWidthInBytes(typeElementType(Ty)) * CHAR_BIT;
 }
 
-} // end of anonymous namespace
-
-const char *InstARM32::getWidthString(Type Ty) {
+const char *getWidthString(Type Ty) {
   return TypeARM32Attributes[Ty].WidthString;
 }
 
-const char *InstARM32::getVecWidthString(Type Ty) {
-  return TypeARM32Attributes[Ty].VecWidthString;
+const char *getFpWidthString(Type Ty) {
+  return TypeARM32Attributes[Ty].FpWidthString;
 }
 
+const char *getSVecWidthString(Type Ty) {
+  return TypeARM32Attributes[Ty].SVecWidthString;
+}
+
+const char *getUVecWidthString(Type Ty) {
+  return TypeARM32Attributes[Ty].UVecWidthString;
+}
+} // end of anonymous namespace
+
 const char *InstARM32Pred::predString(CondARM32::Cond Pred) {
   return InstARM32CondAttributes[Pred].EmitString;
 }
 
 void InstARM32Pred::dumpOpcodePred(Ostream &Str, const char *Opcode,
                                    Type Ty) const {
   Str << Opcode << getPredicate() << "." << Ty;
 }
 
 CondARM32::Cond InstARM32::getOppositeCondition(CondARM32::Cond Cond) {
@@ skipping 50 matching lines @@
   Type SrcTy = Instr->getSrc(0)->getType();
   Str << "\t" << Opcode;
   if (NeedsWidthSuffix)
     Str << getWidthString(SrcTy);
   Str << Instr->getPredicate() << "\t";
   Instr->getDest()->emit(Func);
   Str << ", ";
   Instr->getSrc(0)->emit(Func);
 }
 
-void InstARM32Pred::emitUnaryopFP(const char *Opcode,
+void InstARM32Pred::emitUnaryopFP(const char *Opcode, FPSign Sign,
                                   const InstARM32Pred *Instr, const Cfg *Func) {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Instr->getSrcSize() == 1);
   Type SrcTy = Instr->getSrc(0)->getType();
-  Str << "\t" << Opcode << Instr->getPredicate() << getVecWidthString(SrcTy)
-      << "\t";
+  Str << "\t" << Opcode << Instr->getPredicate();
+  switch (Sign) {
+  case FS_None:
+    Str << getFpWidthString(SrcTy);
+    break;
+  case FS_Signed:
+    Str << getSVecWidthString(SrcTy);
+    break;
+  case FS_Unsigned:
+    Str << getUVecWidthString(SrcTy);
+    break;
+  }
+  Str << "\t";
   Instr->getDest()->emit(Func);
   Str << ", ";
   Instr->getSrc(0)->emit(Func);
 }
 
 void InstARM32Pred::emitTwoAddr(const char *Opcode, const InstARM32Pred *Instr,
                                 const Cfg *Func) {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
@@ skipping 15 matching lines @@
   assert(Instr->getSrcSize() == 2);
   Str << "\t" << Opcode << (SetFlags ? "s" : "") << Instr->getPredicate()
       << "\t";
   Instr->getDest()->emit(Func);
   Str << ", ";
   Instr->getSrc(0)->emit(Func);
   Str << ", ";
   Instr->getSrc(1)->emit(Func);
 }
 
-void InstARM32::emitThreeAddrFP(const char *Opcode, const InstARM32 *Instr,
-                                const Cfg *Func) {
+void InstARM32::emitThreeAddrFP(const char *Opcode, FPSign SignType,
+                                const InstARM32 *Instr, const Cfg *Func) {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Instr->getSrcSize() == 2);
-  Str << "\t" << Opcode << getVecWidthString(Instr->getDest()->getType())
-      << "\t";
+  Str << "\t" << Opcode;
+  switch (SignType) {

[Karl, 2016/04/13 16:17:36]

This switch appears in multiple places. Consider factoring out into a helper
function?

[John, 2016/04/15 13:20:56]

Done.

+  case FS_None:
+    Str << getFpWidthString(Instr->getDest()->getType());
+    break;
+  case FS_Signed:
+    Str << getSVecWidthString(Instr->getDest()->getType());
+    break;
+  case FS_Unsigned:
+    Str << getUVecWidthString(Instr->getDest()->getType());
+    break;
+  }
+  Str << "\t";
   Instr->getDest()->emit(Func);
   Str << ", ";
   Instr->getSrc(0)->emit(Func);
   Str << ", ";
   Instr->getSrc(1)->emit(Func);
 }
 
-void InstARM32::emitFourAddrFP(const char *Opcode, const InstARM32 *Instr,
-                               const Cfg *Func) {
+void InstARM32::emitFourAddrFP(const char *Opcode, FPSign SignType,
+                               const InstARM32 *Instr, const Cfg *Func) {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Instr->getSrcSize() == 3);
   assert(Instr->getSrc(0) == Instr->getDest());
-  Str << "\t" << Opcode << getVecWidthString(Instr->getDest()->getType())
-      << "\t";
+  Str << "\t" << Opcode;
+  switch (SignType) {
+  case FS_None:
+    Str << getFpWidthString(Instr->getDest()->getType());
+    break;
+  case FS_Signed:
+    Str << getSVecWidthString(Instr->getDest()->getType());
+    break;
+  case FS_Unsigned:
+    Str << getUVecWidthString(Instr->getDest()->getType());
+    break;
+  }
+  Str << "\t";
   Instr->getDest()->emit(Func);
   Str << ", ";
   Instr->getSrc(1)->emit(Func);
   Str << ", ";
   Instr->getSrc(2)->emit(Func);
 }
 
 void InstARM32Pred::emitFourAddr(const char *Opcode, const InstARM32Pred *Instr,
                                  const Cfg *Func) {
   if (!BuildDefs::dump())
@@ skipping 18 matching lines @@
 template <InstARM32::InstKindARM32 K>
 void InstARM32FourAddrFP<K>::emitIAS(const Cfg *Func) const {
   emitUsingTextFixup(Func);
 }
 
 template <InstARM32::InstKindARM32 K>
 void InstARM32ThreeAddrFP<K>::emitIAS(const Cfg *Func) const {
   emitUsingTextFixup(Func);
 }
 
+template <InstARM32::InstKindARM32 K>
+void InstARM32ThreeAddrSignAwareFP<K>::emitIAS(const Cfg *Func) const {
+  InstARM32::emitUsingTextFixup(Func);
+}
+
 template <> void InstARM32Mla::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 3);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   Asm->mla(getDest(), getSrc(0), getSrc(1), getSrc(2), getPredicate());
   if (Asm->needsTextFixup())
     emitUsingTextFixup(Func);
 }
 
 template <> void InstARM32Mls::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 3);
@@ skipping 463 matching lines @@
     Asm->vmlss(getDest(), getSrc(1), getSrc(2), CondARM32::AL);
     assert(!Asm->needsTextFixup());
     return;
   case IceType_f64:
     Asm->vmlsd(getDest(), getSrc(1), getSrc(2), CondARM32::AL);
     assert(!Asm->needsTextFixup());
     return;
   }
 }
 
+template <> void InstARM32Vneg::emitIAS(const Cfg *Func) const {
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  const Variable *Dest = getDest();
+  const Type DestTy = Dest->getType();
+  switch (Dest->getType()) {
+  default:
+    llvm::report_fatal_error("Vneg not defined on type " +
+                             typeStdString(Dest->getType()));
+  case IceType_v4i1:
+  case IceType_v8i1:
+  case IceType_v16i1:
+  case IceType_v16i8:
+  case IceType_v8i16:
+  case IceType_v4i32:
+  case IceType_v4f32: {
+    const Type ElmtTy = typeElementType(DestTy);
+    Asm->vnegqs(ElmtTy, Dest, getSrc(0));

[Karl, 2016/04/13 16:17:36]

Is it necessary to factor out ElmtTy here and pass into vnegqs? Why not have
vnegqs do this?

[John, 2016/04/15 13:20:56]

No, it is not, but there is precedent in this file (i.e., vaddqi, vmulqi, and
vsubqi), so I went for consistency. Maybe this should be cleaned (follow up cl)?
Let me know, and I will make this change. :)

+  } break;
+  }
+}
+
 template <> void InstARM32Vorr::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Variable *Dest = getDest();
   switch (Dest->getType()) {
   default:
     llvm::report_fatal_error("Vorr not defined on type " +
                              typeStdString(Dest->getType()));
   case IceType_v4i1:
   case IceType_v8i1:
   case IceType_v16i1:
   case IceType_v16i8:
   case IceType_v8i16:
   case IceType_v4i32:
     Asm->vorrq(Dest, getSrc(0), getSrc(1));
   }
   assert(!Asm->needsTextFixup());
 }
 
+template <> void InstARM32Vshl::emitIAS(const Cfg *Func) const {
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  const Variable *Dest = getDest();
+  const Type DestTy = Dest->getType();
+  switch (DestTy) {
+  default:
+    llvm::report_fatal_error("Vshl not defined on type " +
+                             typeStdString(Dest->getType()));
+  case IceType_v4i1:
+  case IceType_v8i1:
+  case IceType_v16i1:
+  case IceType_v16i8:
+  case IceType_v8i16:
+  case IceType_v4i32: {
+    const Type ElmtTy = typeElementType(DestTy);
+    assert(Sign != InstARM32::FS_None);
+    switch (Sign) {
+    case InstARM32::FS_None: // defaults to unsigned.
+    case InstARM32::FS_Unsigned:
+      Asm->vshlqu(ElmtTy, Dest, getSrc(0), getSrc(1));

[Karl, 2016/04/13 16:17:36]

Similar question here. Should we be forcing the passing of ElmtTy to vshlqu and
vshlqi when they get get it from Dest?

[John, 2016/04/15 13:20:56]

Acknowledged.

+      break;
+    case InstARM32::FS_Signed:
+      Asm->vshlqi(ElmtTy, Dest, getSrc(0), getSrc(1));
+      break;
+    }
+  } break;
+  }
+}
+
 template <> void InstARM32Vsub::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Variable *Dest = getDest();
   Type DestTy = Dest->getType();
   switch (DestTy) {
   default:
     llvm::report_fatal_error("Vsub not defined on type " +
                              typeStdString(DestTy));
   case IceType_v16i8:
   case IceType_v8i16:
@@ skipping 599 matching lines @@
 template <> const char *InstARM32Udiv::Opcode = "udiv";
 // FP
 template <> const char *InstARM32Vadd::Opcode = "vadd";
 template <> const char *InstARM32Vand::Opcode = "vand";
 template <> const char *InstARM32Vdiv::Opcode = "vdiv";
 template <> const char *InstARM32Veor::Opcode = "veor";
 template <> const char *InstARM32Vmla::Opcode = "vmla";
 template <> const char *InstARM32Vmls::Opcode = "vmls";
 template <> const char *InstARM32Vmul::Opcode = "vmul";
 template <> const char *InstARM32Vorr::Opcode = "vorr";
+template <> const char *InstARM32UnaryopFP<InstARM32::Vneg>::Opcode = "vneg";
+template <> const char *InstARM32ThreeAddrFP<InstARM32::Vshl>::Opcode = "vshl";
 template <> const char *InstARM32Vsub::Opcode = "vsub";
 // Four-addr ops
 template <> const char *InstARM32Mla::Opcode = "mla";
 template <> const char *InstARM32Mls::Opcode = "mls";
 // Cmp-like ops
 template <> const char *InstARM32Cmn::Opcode = "cmn";
 template <> const char *InstARM32Cmp::Opcode = "cmp";
 template <> const char *InstARM32Tst::Opcode = "tst";
 
 void InstARM32::dump(const Cfg *Func) const {
@@ skipping 85 matching lines @@
 
   Type Ty = Dest->getType();
   const bool IsVector = isVectorType(Ty);
   const bool IsScalarFP = isScalarFloatingType(Ty);
   const bool CoreVFPMove = isMoveBetweenCoreAndVFPRegisters(Dest, Src0);
   const bool IsVMove = (IsVector || IsScalarFP || CoreVFPMove);
   const char *Opcode = IsVMove ? "vmov" : "mov";
   // when vmov{c}'ing, we need to emit a width string. Otherwise, the
   // assembler might be tempted to assume we want a vector vmov{c}, and that
   // is disallowed because ARM.
-  const char *WidthString = !CoreVFPMove ? getVecWidthString(Ty) : "";
+  const char *WidthString = !CoreVFPMove ? getFpWidthString(Ty) : "";
   CondARM32::Cond Cond = getPredicate();
   if (IsVector)
     assert(CondARM32::isUnconditional(Cond) &&
            "Moves on vectors must be unconditional!");
   Str << "\t" << Opcode;
   if (IsVMove) {
     Str << Cond << WidthString;
   } else {
     Str << WidthString << Cond;
   }
@@ skipping 509 matching lines @@
   Asm->uxt(getDest(), getSrc(0), getPredicate());
   if (Asm->needsTextFixup())
     emitUsingTextFixup(Func);
 }
 
 template <InstARM32::InstKindARM32 K>
 void InstARM32UnaryopFP<K>::emitIAS(const Cfg *Func) const {
   emitUsingTextFixup(Func);
 }
 
+template <InstARM32::InstKindARM32 K>
+void InstARM32UnaryopSignAwareFP<K>::emitIAS(const Cfg *Func) const {
+  InstARM32::emitUsingTextFixup(Func);
+}
+
 template <> void InstARM32Vsqrt::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Operand *Dest = getDest();
   switch (Dest->getType()) {
   case IceType_f32:
     Asm->vsqrts(Dest, getSrc(0), getPredicate());
     break;
   case IceType_f64:
     Asm->vsqrtd(Dest, getSrc(0), getPredicate());
@@ skipping 391 matching lines @@
       << "vcvt" << getPredicate() << vcvtVariantSuffix(Variant) << " ";
   dumpSources(Func);
 }
 
 void InstARM32Vcmp::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   Str << "\t"
-         "vcmp" << getPredicate() << getVecWidthString(getSrc(0)->getType())
+         "vcmp" << getPredicate() << getFpWidthString(getSrc(0)->getType())
       << "\t";
   getSrc(0)->emit(Func);
   Str << ", ";
   getSrc(1)->emit(Func);
 }
 
 void InstARM32Vcmp::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   const Operand *Src0 = getSrc(0);
   const Type Ty = Src0->getType();
@@ skipping 23 matching lines @@
       llvm::report_fatal_error("Vcvt on non floating value");
     }
   }
   assert(!Asm->needsTextFixup());
 }
 
 void InstARM32Vcmp::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
-  Str << "vcmp" << getPredicate() << getVecWidthString(getSrc(0)->getType());
+  Str << "vcmp" << getPredicate() << getFpWidthString(getSrc(0)->getType());
   dumpSources(Func);
 }
 
 void InstARM32Vmrs::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 0);
   Str << "\t"
          "vmrs" << getPredicate() << "\t"
@@ skipping 15 matching lines @@
   Str << "APSR{n,z,v,c} = vmrs" << getPredicate() << "\t"
                                                      "FPSCR{n,z,c,v}";
 }
 
 void InstARM32Vabs::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Str << "\t"
-         "vabs" << getPredicate() << getVecWidthString(getSrc(0)->getType())
+         "vabs" << getPredicate() << getFpWidthString(getSrc(0)->getType())
       << "\t";
   getDest()->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
 void InstARM32Vabs::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Variable *Dest = getDest();
@@ skipping 13 matching lines @@
     Asm->vabsq(Dest, getSrc(0));
   }
   assert(!Asm->needsTextFixup());
 }
 
 void InstARM32Vabs::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   dumpDest(Func);
-  Str << " = vabs" << getPredicate() << getVecWidthString(getSrc(0)->getType());
+  Str << " = vabs" << getPredicate() << getFpWidthString(getSrc(0)->getType());
 }
 
 void InstARM32Dmb::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 0);
   Str << "\t"
          "dmb"
          "\t"
@@ skipping 179 matching lines @@
   case IceType_f32:
     Str << "#" << materializeFloatImmediate(ModifiedImm)
         << " @ Modified: " << ModifiedImm;
     break;
   }
 }
 
 void OperandARM32FlexFpImm::dump(const Cfg * /*Func*/, Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
-  Str << "#" << materializeFloatImmediate(ModifiedImm)
-      << InstARM32::getVecWidthString(Ty);
+  Str << "#" << materializeFloatImmediate(ModifiedImm) << getFpWidthString(Ty);
 }
 
 void OperandARM32FlexFpZero::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   switch (Ty) {
   default:
     llvm::report_fatal_error("Invalid flex fp imm type.");
   case IceType_f64:
   case IceType_f32:
     Str << "#0.0";
   }
 }
 
 void OperandARM32FlexFpZero::dump(const Cfg * /*Func*/, Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
-  Str << "#0.0" << InstARM32::getVecWidthString(Ty);
+  Str << "#0.0" << getFpWidthString(Ty);
 }
 
 void OperandARM32FlexReg::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   getReg()->emit(Func);
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     getShiftAmt()->emit(Func);
@@ skipping 34 matching lines @@
 template class InstARM32ThreeAddrGPR<InstARM32::Sdiv>;
 template class InstARM32ThreeAddrGPR<InstARM32::Sub>;
 template class InstARM32ThreeAddrGPR<InstARM32::Udiv>;
 
 template class InstARM32ThreeAddrFP<InstARM32::Vadd>;
 template class InstARM32ThreeAddrFP<InstARM32::Vdiv>;
 template class InstARM32ThreeAddrFP<InstARM32::Veor>;
 template class InstARM32FourAddrFP<InstARM32::Vmla>;
 template class InstARM32FourAddrFP<InstARM32::Vmls>;
 template class InstARM32ThreeAddrFP<InstARM32::Vmul>;
+template class InstARM32UnaryopSignAwareFP<InstARM32::Vneg>;
+template class InstARM32ThreeAddrSignAwareFP<InstARM32::Vshl>;
 template class InstARM32ThreeAddrFP<InstARM32::Vsub>;
 
 template class InstARM32LoadBase<InstARM32::Ldr>;
 template class InstARM32LoadBase<InstARM32::Ldrex>;
 
 template class InstARM32TwoAddrGPR<InstARM32::Movt>;
 
 template class InstARM32UnaryopGPR<InstARM32::Movw, false>;
 template class InstARM32UnaryopGPR<InstARM32::Clz, false>;
 template class InstARM32UnaryopGPR<InstARM32::Mvn, false>;
 template class InstARM32UnaryopGPR<InstARM32::Rbit, false>;
 template class InstARM32UnaryopGPR<InstARM32::Rev, false>;
 template class InstARM32UnaryopGPR<InstARM32::Sxt, true>;
 template class InstARM32UnaryopGPR<InstARM32::Uxt, true>;
 template class InstARM32UnaryopFP<InstARM32::Vsqrt>;
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice