MIPS64: Fix rotate instructions in simulator

src/mips64/simulator-mips64.cc

Index: src/mips64/simulator-mips64.cc
diff --git a/src/mips64/simulator-mips64.cc b/src/mips64/simulator-mips64.cc
index 9519865c8231eab71bcc54840827e82537b702fe..e225b8482c7f9738899af2abcabd113caa018fb9 100644
--- a/src/mips64/simulator-mips64.cc
+++ b/src/mips64/simulator-mips64.cc
@@ -3431,10 +3431,37 @@ void Simulator::DecodeTypeRegisterSPECIAL() {
       SetResult(rd_reg(), alu_out);
       break;
     case DSRL:
-      SetResult(rd_reg(), rt_u() >> sa());
+      if (rs_reg() == 0) {
+        // Regular logical right shift of a word by a fixed number of
+        // bits instruction. RS field is always equal to 0.
+        // Sign-extend the 64-bit result.

[balazs.kilvady, 2016/04/12 10:18:00]

Is it realy necessary to use double conversion in the bellow line? If we need
sign extension then a 'rt_u() >> sa()' would not be enough? Have you tested
both?

[Marija Antic, 2016/04/12 12:59:16]

Done.

+        alu_out = static_cast<int64_t>(static_cast<uint64_t>(rt_u()) >> sa());

[Ilija.Pavlovic1, 2016/04/12 12:31:32]

rt_u() already returns uint64_t.

+      } else {
+        // Logical right-rotate of a word by a fixed number of bits. This
+        // is special case of SRL instruction, added in MIPS32 Release 2.
+        // RS field is equal to 00001.
+        alu_out = static_cast<int64_t>(
+            base::bits::RotateRight64(static_cast<const uint64_t>(rt_u()),
+                                      static_cast<const uint64_t>(sa())));

[balazs.kilvady, 2016/04/12 10:18:00]

RotateRight64() gets its inputs by value so converting it to const is useless at
here, also rt_u() is uint64_t already. I hope sa() also :)

[Marija Antic, 2016/04/12 12:59:16]

Done.

+      }
+      SetResult(rd_reg(), alu_out);
       break;

[Ilija.Pavlovic1, 2016/04/12 12:31:32]

Rs field has defined values 0 and 1. Other values are not defined. Therefore I
suggest following logic for this:
case DSRL: {
  switch (rs_reg()) {
    case 0:
       // DSRL
       break;
    case 1:
       // DROTR
       break;
    default:
       UNREACHABLE();
  }
  SetResult(rd_reg(), alu_out);
  break;
}

[Marija Antic, 2016/04/12 12:59:16]

Done.

     case DSRL32:
-      SetResult(rd_reg(), rt_u() >> sa() >> 32);
+      if (rs_reg() == 0) {
+        // Regular logical right shift of a word by a fixed number of
+        // bits instruction. RS field is always equal to 0.
+        // Sign-extend the 64-bit result.
+        alu_out =
+            static_cast<int64_t>(static_cast<uint64_t>(rt_u()) >> sa() >> 32);
+      } else {
+        // Logical right-rotate of a word by a fixed number of bits. This
+        // is special case of SRL instruction, added in MIPS32 Release 2.
+        // RS field is equal to 00001.
+        alu_out = static_cast<int64_t>(
+            base::bits::RotateRight64(static_cast<const uint64_t>(rt_u()),
+                                      static_cast<const uint64_t>(sa()) + 32));
+      }

[balazs.kilvady, 2016/04/12 10:18:00]

Same conversion notes like above.

+      SetResult(rd_reg(), alu_out);
       break;

[Ilija.Pavlovic1, 2016/04/12 12:31:32]

To use "switch-case" as for DSRL.

[Marija Antic, 2016/04/12 12:59:16]

Keeping it with rs_reg() (it does the same), in order to resemble the rest of
simulator code.

On 2016/04/12 12:31:32, Ilija.Pavlovic1 wrote:

     case SRA:
       SetResult(rd_reg(), (int32_t)rt() >> sa());