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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> | 5 #include <limits.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdlib.h> | 7 #include <stdlib.h> |
8 #include <cmath> | 8 #include <cmath> |
9 | 9 |
10 #if V8_TARGET_ARCH_MIPS64 | 10 #if V8_TARGET_ARCH_MIPS64 |
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3412 SetResult(rd_reg(), rt() << sa()); | 3412 SetResult(rd_reg(), rt() << sa()); |
3413 break; | 3413 break; |
3414 case DSLL32: | 3414 case DSLL32: |
3415 SetResult(rd_reg(), rt() << sa() << 32); | 3415 SetResult(rd_reg(), rt() << sa() << 32); |
3416 break; | 3416 break; |
3417 case SRL: | 3417 case SRL: |
3418 if (rs_reg() == 0) { | 3418 if (rs_reg() == 0) { |
3419 // Regular logical right shift of a word by a fixed number of | 3419 // Regular logical right shift of a word by a fixed number of |
3420 // bits instruction. RS field is always equal to 0. | 3420 // bits instruction. RS field is always equal to 0. |
3421 // Sign-extend the 32-bit result. | 3421 // Sign-extend the 32-bit result. |
3422 alu_out = static_cast<int32_t>(static_cast<uint32_t>(rt_u()) >> sa()); | 3422 alu_out = static_cast<int32_t>(static_cast<uint32_t>(rt_u()) >> sa()); |
balazs.kilvady
2016/04/12 13:14:33
I see. A lot of unnecessary casting existed alread
| |
3423 } else { | 3423 } else if (rs_reg() == 1) { |
3424 // Logical right-rotate of a word by a fixed number of bits. This | 3424 // Logical right-rotate of a word by a fixed number of bits. This |
3425 // is special case of SRL instruction, added in MIPS32 Release 2. | 3425 // is special case of SRL instruction, added in MIPS32 Release 2. |
3426 // RS field is equal to 00001. | 3426 // RS field is equal to 00001. |
3427 alu_out = static_cast<int32_t>( | 3427 alu_out = static_cast<int32_t>( |
3428 base::bits::RotateRight32(static_cast<const uint32_t>(rt_u()), | 3428 base::bits::RotateRight32(static_cast<const uint32_t>(rt_u()), |
3429 static_cast<const uint32_t>(sa()))); | 3429 static_cast<const uint32_t>(sa()))); |
balazs.kilvady
2016/04/12 13:14:33
I see. A lot of unecessary comment existed already
| |
3430 } else { | |
3431 UNREACHABLE(); | |
3430 } | 3432 } |
3431 SetResult(rd_reg(), alu_out); | 3433 SetResult(rd_reg(), alu_out); |
3432 break; | 3434 break; |
3433 case DSRL: | 3435 case DSRL: |
3434 SetResult(rd_reg(), rt_u() >> sa()); | 3436 if (rs_reg() == 0) { |
3437 // Regular logical right shift of a word by a fixed number of | |
3438 // bits instruction. RS field is always equal to 0. | |
3439 // Sign-extend the 64-bit result. | |
3440 alu_out = static_cast<int64_t>(rt_u() >> sa()); | |
3441 } else if (rs_reg() == 1) { | |
3442 // Logical right-rotate of a word by a fixed number of bits. This | |
3443 // is special case of SRL instruction, added in MIPS32 Release 2. | |
3444 // RS field is equal to 00001. | |
3445 alu_out = static_cast<int64_t>(base::bits::RotateRight64(rt_u(), sa())); | |
3446 } else { | |
3447 UNREACHABLE(); | |
3448 } | |
3449 SetResult(rd_reg(), alu_out); | |
3435 break; | 3450 break; |
3436 case DSRL32: | 3451 case DSRL32: |
3437 SetResult(rd_reg(), rt_u() >> sa() >> 32); | 3452 if (rs_reg() == 0) { |
3453 // Regular logical right shift of a word by a fixed number of | |
3454 // bits instruction. RS field is always equal to 0. | |
3455 // Sign-extend the 64-bit result. | |
3456 alu_out = static_cast<int64_t>(rt_u() >> sa() >> 32); | |
3457 } else if (rs_reg() == 1) { | |
3458 // Logical right-rotate of a word by a fixed number of bits. This | |
3459 // is special case of SRL instruction, added in MIPS32 Release 2. | |
3460 // RS field is equal to 00001. | |
3461 alu_out = | |
3462 static_cast<int64_t>(base::bits::RotateRight64(rt_u(), sa() + 32)); | |
3463 } else { | |
3464 UNREACHABLE(); | |
3465 } | |
3466 SetResult(rd_reg(), alu_out); | |
3438 break; | 3467 break; |
3439 case SRA: | 3468 case SRA: |
3440 SetResult(rd_reg(), (int32_t)rt() >> sa()); | 3469 SetResult(rd_reg(), (int32_t)rt() >> sa()); |
3441 break; | 3470 break; |
3442 case DSRA: | 3471 case DSRA: |
3443 SetResult(rd_reg(), rt() >> sa()); | 3472 SetResult(rd_reg(), rt() >> sa()); |
3444 break; | 3473 break; |
3445 case DSRA32: | 3474 case DSRA32: |
3446 SetResult(rd_reg(), rt() >> sa() >> 32); | 3475 SetResult(rd_reg(), rt() >> sa() >> 32); |
3447 break; | 3476 break; |
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3463 alu_out = static_cast<int32_t>( | 3492 alu_out = static_cast<int32_t>( |
3464 base::bits::RotateRight32(static_cast<const uint32_t>(rt_u()), | 3493 base::bits::RotateRight32(static_cast<const uint32_t>(rt_u()), |
3465 static_cast<const uint32_t>(rs_u()))); | 3494 static_cast<const uint32_t>(rs_u()))); |
3466 } | 3495 } |
3467 SetResult(rd_reg(), alu_out); | 3496 SetResult(rd_reg(), alu_out); |
3468 break; | 3497 break; |
3469 case DSRLV: | 3498 case DSRLV: |
3470 if (sa() == 0) { | 3499 if (sa() == 0) { |
3471 // Regular logical right-shift of a word by a variable number of | 3500 // Regular logical right-shift of a word by a variable number of |
3472 // bits instruction. SA field is always equal to 0. | 3501 // bits instruction. SA field is always equal to 0. |
3473 alu_out = rt_u() >> rs(); | 3502 alu_out = static_cast<int64_t>(rt_u() >> rs()); |
3474 } else { | 3503 } else { |
3475 // Logical right-rotate of a word by a variable number of bits. | 3504 // Logical right-rotate of a word by a variable number of bits. |
3476 // This is special case od SRLV instruction, added in MIPS32 | 3505 // This is special case od SRLV instruction, added in MIPS32 |
3477 // Release 2. SA field is equal to 00001. | 3506 // Release 2. SA field is equal to 00001. |
3478 alu_out = base::bits::RotateRight64(rt_u(), rs_u()); | 3507 alu_out = |
3508 static_cast<int64_t>(base::bits::RotateRight64(rt_u(), rs_u())); | |
3479 } | 3509 } |
3480 SetResult(rd_reg(), alu_out); | 3510 SetResult(rd_reg(), alu_out); |
3481 break; | 3511 break; |
3482 case SRAV: | 3512 case SRAV: |
3483 SetResult(rd_reg(), (int32_t)rt() >> rs()); | 3513 SetResult(rd_reg(), (int32_t)rt() >> rs()); |
3484 break; | 3514 break; |
3485 case DSRAV: | 3515 case DSRAV: |
3486 SetResult(rd_reg(), rt() >> rs()); | 3516 SetResult(rd_reg(), rt() >> rs()); |
3487 break; | 3517 break; |
3488 case LSA: { | 3518 case LSA: { |
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4846 } | 4876 } |
4847 | 4877 |
4848 | 4878 |
4849 #undef UNSUPPORTED | 4879 #undef UNSUPPORTED |
4850 } // namespace internal | 4880 } // namespace internal |
4851 } // namespace v8 | 4881 } // namespace v8 |
4852 | 4882 |
4853 #endif // USE_SIMULATOR | 4883 #endif // USE_SIMULATOR |
4854 | 4884 |
4855 #endif // V8_TARGET_ARCH_MIPS64 | 4885 #endif // V8_TARGET_ARCH_MIPS64 |
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