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Issue 1880953002: MIPS64: Fix rotate instructions in simulator (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Address comments and add tests Created 4 years, 8 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // A Disassembler object is used to disassemble a block of code instruction by 5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be 6 // instruction. The default implementation of the NameConverter object can be
7 // overriden to modify register names or to do symbol lookup on addresses. 7 // overriden to modify register names or to do symbol lookup on addresses.
8 // 8 //
9 // The example below will disassemble a block of code and print it to stdout. 9 // The example below will disassemble a block of code and print it to stdout.
10 // 10 //
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1155 } 1155 }
1156 } 1156 }
1157 break; 1157 break;
1158 case DSLL32: 1158 case DSLL32:
1159 Format(instr, "dsll32 'rd, 'rt, 'sa"); 1159 Format(instr, "dsll32 'rd, 'rt, 'sa");
1160 break; 1160 break;
1161 case SRL: 1161 case SRL:
1162 if (instr->RsValue() == 0) { 1162 if (instr->RsValue() == 0) {
1163 Format(instr, "srl 'rd, 'rt, 'sa"); 1163 Format(instr, "srl 'rd, 'rt, 'sa");
1164 } else { 1164 } else {
1165 if (kArchVariant == kMips64r2) { 1165 Format(instr, "rotr 'rd, 'rt, 'sa");
1166 Format(instr, "rotr 'rd, 'rt, 'sa");
1167 } else {
1168 Unknown(instr);
1169 }
1170 } 1166 }
1171 break; 1167 break;
1172 case DSRL: 1168 case DSRL:
1173 if (instr->RsValue() == 0) { 1169 if (instr->RsValue() == 0) {
1174 Format(instr, "dsrl 'rd, 'rt, 'sa"); 1170 Format(instr, "dsrl 'rd, 'rt, 'sa");
1175 } else { 1171 } else {
1176 if (kArchVariant == kMips64r2) { 1172 Format(instr, "drotr 'rd, 'rt, 'sa");
1177 Format(instr, "drotr 'rd, 'rt, 'sa");
1178 } else {
1179 Unknown(instr);
1180 }
1181 } 1173 }
1182 break; 1174 break;
1183 case DSRL32: 1175 case DSRL32:
1184 Format(instr, "dsrl32 'rd, 'rt, 'sa"); 1176 if (instr->RsValue() == 0) {
1177 Format(instr, "dsrl32 'rd, 'rt, 'sa");
1178 } else {
1179 Format(instr, "drotr32 'rd, 'rt, 'sa");
1180 }
1185 break; 1181 break;
1186 case SRA: 1182 case SRA:
1187 Format(instr, "sra 'rd, 'rt, 'sa"); 1183 Format(instr, "sra 'rd, 'rt, 'sa");
1188 break; 1184 break;
1189 case DSRA: 1185 case DSRA:
1190 Format(instr, "dsra 'rd, 'rt, 'sa"); 1186 Format(instr, "dsra 'rd, 'rt, 'sa");
1191 break; 1187 break;
1192 case DSRA32: 1188 case DSRA32:
1193 Format(instr, "dsra32 'rd, 'rt, 'sa"); 1189 Format(instr, "dsra32 'rd, 'rt, 'sa");
1194 break; 1190 break;
1195 case SLLV: 1191 case SLLV:
1196 Format(instr, "sllv 'rd, 'rt, 'rs"); 1192 Format(instr, "sllv 'rd, 'rt, 'rs");
1197 break; 1193 break;
1198 case DSLLV: 1194 case DSLLV:
1199 Format(instr, "dsllv 'rd, 'rt, 'rs"); 1195 Format(instr, "dsllv 'rd, 'rt, 'rs");
1200 break; 1196 break;
1201 case SRLV: 1197 case SRLV:
1202 if (instr->SaValue() == 0) { 1198 if (instr->SaValue() == 0) {
1203 Format(instr, "srlv 'rd, 'rt, 'rs"); 1199 Format(instr, "srlv 'rd, 'rt, 'rs");
1204 } else { 1200 } else {
1205 if (kArchVariant == kMips64r2) { 1201 Format(instr, "rotrv 'rd, 'rt, 'rs");
1206 Format(instr, "rotrv 'rd, 'rt, 'rs");
1207 } else {
1208 Unknown(instr);
1209 }
1210 } 1202 }
1211 break; 1203 break;
1212 case DSRLV: 1204 case DSRLV:
1213 if (instr->SaValue() == 0) { 1205 if (instr->SaValue() == 0) {
1214 Format(instr, "dsrlv 'rd, 'rt, 'rs"); 1206 Format(instr, "dsrlv 'rd, 'rt, 'rs");
1215 } else { 1207 } else {
1216 if (kArchVariant == kMips64r2) { 1208 Format(instr, "drotrv 'rd, 'rt, 'rs");
1217 Format(instr, "drotrv 'rd, 'rt, 'rs");
1218 } else {
1219 Unknown(instr);
1220 }
1221 } 1209 }
1222 break; 1210 break;
1223 case SRAV: 1211 case SRAV:
1224 Format(instr, "srav 'rd, 'rt, 'rs"); 1212 Format(instr, "srav 'rd, 'rt, 'rs");
1225 break; 1213 break;
1226 case DSRAV: 1214 case DSRAV:
1227 Format(instr, "dsrav 'rd, 'rt, 'rs"); 1215 Format(instr, "dsrav 'rd, 'rt, 'rs");
1228 break; 1216 break;
1229 case LSA: 1217 case LSA:
1230 Format(instr, "lsa 'rd, 'rt, 'rs, 'sa2"); 1218 Format(instr, "lsa 'rd, 'rt, 'rs, 'sa2");
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2015 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 2003 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
2016 } 2004 }
2017 } 2005 }
2018 2006
2019 2007
2020 #undef UNSUPPORTED 2008 #undef UNSUPPORTED
2021 2009
2022 } // namespace disasm 2010 } // namespace disasm
2023 2011
2024 #endif // V8_TARGET_ARCH_MIPS64 2012 #endif // V8_TARGET_ARCH_MIPS64
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