MIPS64: Fix rotate instructions in simulator

src/mips64/disasm-mips64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 1144 matching lines @@
         }
       }
       break;
     case DSLL32:
       Format(instr, "dsll32  'rd, 'rt, 'sa");
       break;
     case SRL:
       if (instr->RsValue() == 0) {
         Format(instr, "srl     'rd, 'rt, 'sa");
       } else {
-        if (kArchVariant == kMips64r2) {
-          Format(instr, "rotr    'rd, 'rt, 'sa");
-        } else {
-          Unknown(instr);
-        }
+        Format(instr, "rotr    'rd, 'rt, 'sa");
       }
       break;
     case DSRL:
       if (instr->RsValue() == 0) {
         Format(instr, "dsrl    'rd, 'rt, 'sa");
       } else {
-        if (kArchVariant == kMips64r2) {
-          Format(instr, "drotr   'rd, 'rt, 'sa");
-        } else {
-          Unknown(instr);
-        }
+        Format(instr, "drotr   'rd, 'rt, 'sa");
       }
       break;
     case DSRL32:

[Ilija.Pavlovic1, 2016/04/12 12:31:31]

Missing test cases in test-disassembler-mips64.cc for dsrl32 and drotr32.
Also consider using construction
switch(instr->RsValue()) {...}

[Marija Antic, 2016/04/12 12:59:16]

Done.

-      Format(instr, "dsrl32  'rd, 'rt, 'sa");
+      if (instr->RsValue() == 0) {
+        Format(instr, "dsrl32  'rd, 'rt, 'sa");
+      } else {
+        Format(instr, "drotr32   'rd, 'rt, 'sa");
+      }

[balazs.kilvady, 2016/04/12 10:18:00]

Have you checked the diasm output? Are the number of spaces right in the above 2
Format() lines? It looks like arguments of drotr32 will be shifted to right a
bit.

[Marija Antic, 2016/04/12 12:59:16]

Done.

       break;
     case SRA:
       Format(instr, "sra     'rd, 'rt, 'sa");
       break;
     case DSRA:
       Format(instr, "dsra    'rd, 'rt, 'sa");
       break;
     case DSRA32:
       Format(instr, "dsra32  'rd, 'rt, 'sa");
       break;
     case SLLV:
       Format(instr, "sllv    'rd, 'rt, 'rs");
       break;
     case DSLLV:
       Format(instr, "dsllv   'rd, 'rt, 'rs");
       break;
     case SRLV:
       if (instr->SaValue() == 0) {
         Format(instr, "srlv    'rd, 'rt, 'rs");
       } else {
-        if (kArchVariant == kMips64r2) {
-          Format(instr, "rotrv   'rd, 'rt, 'rs");
-        } else {
-          Unknown(instr);
-        }
+        Format(instr, "rotrv   'rd, 'rt, 'rs");
       }
       break;
     case DSRLV:
       if (instr->SaValue() == 0) {
         Format(instr, "dsrlv   'rd, 'rt, 'rs");
       } else {
-        if (kArchVariant == kMips64r2) {
-          Format(instr, "drotrv  'rd, 'rt, 'rs");
-        } else {
-          Unknown(instr);
-        }
+        Format(instr, "drotrv  'rd, 'rt, 'rs");
       }
       break;
     case SRAV:
       Format(instr, "srav    'rd, 'rt, 'rs");
       break;
     case DSRAV:
       Format(instr, "dsrav   'rd, 'rt, 'rs");
       break;
     case LSA:
       Format(instr, "lsa     'rd, 'rt, 'rs, 'sa2");
@@ skipping 784 matching lines @@
         prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 #undef UNSUPPORTED
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_MIPS64