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| 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// |
| 2 // | 2 // |
| 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a |
| 5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. |
| 6 // | 6 // |
| 7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. |
| 8 // | 8 // |
| 9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// |
| 10 // | 10 // |
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| 412 // ElmtSize = #bits in vector element. | 412 // ElmtSize = #bits in vector element. |
| 413 void vld1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn, | 413 void vld1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn, |
| 414 const TargetInfo &TInfo); | 414 const TargetInfo &TInfo); |
| 415 | 415 |
| 416 void vld1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn, | 416 void vld1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn, |
| 417 const TargetLowering *Lowering) { | 417 const TargetLowering *Lowering) { |
| 418 const TargetInfo TInfo(Lowering); | 418 const TargetInfo TInfo(Lowering); |
| 419 vld1qr(ElmtSize, OpQd, OpRn, TInfo); | 419 vld1qr(ElmtSize, OpQd, OpRn, TInfo); |
| 420 } | 420 } |
| 421 | 421 |
| 422 // Qn[i] = Imm for all i in vector. Returns true iff Imm can be defined as an |
| 423 // Imm8 using AdvSIMDExpandImm(). |
| 424 bool vmovqc(const Operand *OpQd, const ConstantInteger32 *Imm); |
| 425 |
| 422 // Dn = FpImm | 426 // Dn = FpImm |
| 423 void vmovd(const Operand *OpDn, const OperandARM32FlexFpImm *OpFpImm, | 427 void vmovd(const Operand *OpDn, const OperandARM32FlexFpImm *OpFpImm, |
| 424 CondARM32::Cond Cond); | 428 CondARM32::Cond Cond); |
| 425 | 429 |
| 426 // Dd = Dm | 430 // Dd = Dm |
| 427 void vmovdd(const Operand *OpDd, const Variable *OpDm, CondARM32::Cond Cond); | 431 void vmovdd(const Operand *OpDd, const Variable *OpDm, CondARM32::Cond Cond); |
| 428 | 432 |
| 429 // Dm = Rt:Rt2 | 433 // Dm = Rt:Rt2 |
| 430 void vmovdrr(const Operand *OpDm, const Operand *OpRt, const Operand *OpRt2, | 434 void vmovdrr(const Operand *OpDm, const Operand *OpRt, const Operand *OpRt2, |
| 431 CondARM32::Cond Cond); | 435 CondARM32::Cond Cond); |
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| 758 | 762 |
| 759 void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd, | 763 void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd, |
| 760 const Operand *OpSn, const Operand *OpSm, | 764 const Operand *OpSn, const Operand *OpSm, |
| 761 const char *InstName); | 765 const char *InstName); |
| 762 }; | 766 }; |
| 763 | 767 |
| 764 } // end of namespace ARM32 | 768 } // end of namespace ARM32 |
| 765 } // end of namespace Ice | 769 } // end of namespace Ice |
| 766 | 770 |
| 767 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H | 771 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H |
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