Add "vmov.<dt> <Qd>, #<imm>" to integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 197 matching lines @@
 }
 
 IValueT getYInRegXXXXY(IValueT RegXXXXY) { return RegXXXXY & 0x1; }
 
 IValueT getXXXXInRegXXXXY(IValueT RegXXXXY) { return RegXXXXY >> 1; }
 
 IValueT getYInRegYXXXX(IValueT RegYXXXX) { return RegYXXXX >> 4; }
 
 IValueT getXXXXInRegYXXXX(IValueT RegYXXXX) { return RegYXXXX & 0x0f; }
 
+// Figures out Op/Cmode values for given Value. Returns true if able to encode.
+bool encodeAdvSIMDExpandImm(IValueT Value, Type ElmtTy, IValueT &Op,
+                            IValueT &Cmode, IValueT &Imm8) {
+  // TODO(kschimpf): Handle other shifted 8-bit values.
+  constexpr IValueT Imm8Mask = 0xFF;
+  if ((Value & IValueT(~Imm8Mask)) != 0)
+    return false;
+  Imm8 = Value;
+  switch (ElmtTy) {
+  case IceType_i16:
+    Op = 0;
+    Cmode = 8; // 100:0
+    return true;
+  case IceType_i32:
+    Op = 0;
+    Cmode = 0; // 000:0
+    return true;
+  default:
+    return false;
+  }
+}
+
 // Defines layouts of an operand representing a (register) memory address,
 // possibly modified by an immediate value.
 enum EncodedImmAddress {
   // Address modified by a rotated immediate 8-bit value.
   RotatedImm8Address,
 
   // Alternate encoding for RotatedImm8Address, where the offset is divided by 4
   // before encoding.
   RotatedImm8Div4Address,
 
@@ skipping 2475 matching lines @@
   if (encodeAddress(OpAddress, Address, TInfo, NoImmOffsetAddress) !=
       EncodedAsImmRegOffset)
     llvm::report_fatal_error(std::string(Vld1qr) + ": malform memory address");
   const IValueT Rn = mask(Address, kRnShift, 4);
   constexpr IValueT Rm = RegARM32::Reg_pc;
   constexpr IValueT Opcode = B26 | B21;
   constexpr IValueT Align = 0; // use default alignment.
   emitVMem1Op(Opcode, Dd, Rn, Rm, DRegListSize2, ElmtSize, Align, Vld1qr);
 }
 
+bool AssemblerARM32::vmovqc(const Operand *OpQd, const ConstantInteger32 *Imm) {
+  // VMOV (immediate) - ARM section A8.8.320, encoding A1:
+  //   VMOV.<dt> <Qd>, #<Imm>
+  // 1111001x1D000yyyddddcccc01p1zzzz where Qd=Ddddd, Imm=xyyyzzzz, cmode=cccc,
+  // and Op=p.
+  constexpr const char *Vmovc = "vmovc";
+  const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmovc));
+  IValueT Value = Imm->getValue();
+  const Type VecTy = OpQd->getType();
+  if (!isVectorType(VecTy))
+    return false;
+
+  IValueT Op;
+  IValueT Cmode;
+  IValueT Imm8;
+  if (!encodeAdvSIMDExpandImm(Value, typeElementType(VecTy), Op, Cmode, Imm8))
+    return false;
+  if (Op == 0 && mask(Cmode, 0, 1) == 1)
+    return false;
+  if (Op == 1 && Cmode != 13)
+    return false;
+  const IValueT Encoding =
+      (0xF << kConditionShift) | B25 | B23 | B6 | B4 |
+      (mask(Imm8, 7, 1) << 24) | (getYInRegYXXXX(Dd) << 22) |
+      (mask(Imm8, 4, 3) << 16) | (getXXXXInRegYXXXX(Dd) << 12) | (Cmode << 8) |
+      (Op << 5) | mask(Imm8, 0, 4);
+  emitInst(Encoding);
+  return true;
+}
+
 void AssemblerARM32::vmovd(const Operand *OpDd,
                            const OperandARM32FlexFpImm *OpFpImm,
                            CondARM32::Cond Cond) {
   // VMOV (immediate) - ARM section A8.8.339, encoding A2:
   //   vmov<c>.f64 <Dd>, #<imm>
   //
   // cccc11101D11xxxxdddd10110000yyyy where cccc=Cond, ddddD=Sn, xxxxyyyy=imm.
   constexpr const char *Vmovd = "vmovd";
   IValueT Dd = encodeSRegister(OpDd, "Dd", Vmovd);
   IValueT Imm8 = OpFpImm->getModifiedImm();
@@ skipping 477 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice