Subzero. ARM32. Vector casts.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 420 matching lines @@
     Vcvt,
     Vdiv,
     Veor,
     Vmla,
     Vmls,
     Vmrs,
     Vmul,
     Vneg,
     Vorr,
     Vshl,
+    Vshr,
     Vsqrt,
     Vsub
   };
 
   static constexpr size_t InstSize = sizeof(uint32_t);
 
   static CondARM32::Cond getOppositeCondition(CondARM32::Cond Cond);
 
   /// Called inside derived methods emit() to communicate that multiple
   /// instructions are being generated. Used by emitIAS() methods to
@@ skipping 364 matching lines @@
 
 public:
   /// Create a vector/FP binary-op instruction like vadd, and vsub. Everything
   /// must be a register.
   static InstARM32ThreeAddrSignAwareFP *create(Cfg *Func, Variable *Dest,
                                                Variable *Src0, Variable *Src1) {
     return new (Func->allocate<InstARM32ThreeAddrSignAwareFP>())
         InstARM32ThreeAddrSignAwareFP(Func, Dest, Src0, Src1);
   }
 
+  static InstARM32ThreeAddrSignAwareFP *
+  create(Cfg *Func, Variable *Dest, Variable *Src0, ConstantInteger32 *Src1) {
+    return new (Func->allocate<InstARM32ThreeAddrSignAwareFP>())
+        InstARM32ThreeAddrSignAwareFP(Func, Dest, Src0, Src1);
+  }
+
   void emitIAS(const Cfg *Func) const override;
   void setSignType(InstARM32::FPSign SignType) { this->Sign = SignType; }
 
 private:
   InstARM32ThreeAddrSignAwareFP(Cfg *Func, Variable *Dest, Variable *Src0,
-                                Variable *Src1)
+                                Operand *Src1)
       : InstARM32ThreeAddrFP<K>(Func, Dest, Src0, Src1) {}
 };
 
 /// Instructions of the form x := a op1 (y op2 z). E.g., multiply accumulate.
 template <InstARM32::InstKindARM32 K>
 class InstARM32FourAddrGPR : public InstARM32Pred {
   InstARM32FourAddrGPR() = delete;
   InstARM32FourAddrGPR(const InstARM32FourAddrGPR &) = delete;
   InstARM32FourAddrGPR &operator=(const InstARM32FourAddrGPR &) = delete;
 
@@ skipping 145 matching lines @@
 using InstARM32Vadd = InstARM32ThreeAddrFP<InstARM32::Vadd>;
 using InstARM32Vand = InstARM32ThreeAddrFP<InstARM32::Vand>;
 using InstARM32Vdiv = InstARM32ThreeAddrFP<InstARM32::Vdiv>;
 using InstARM32Veor = InstARM32ThreeAddrFP<InstARM32::Veor>;
 using InstARM32Vmla = InstARM32FourAddrFP<InstARM32::Vmla>;
 using InstARM32Vmls = InstARM32FourAddrFP<InstARM32::Vmls>;
 using InstARM32Vmul = InstARM32ThreeAddrFP<InstARM32::Vmul>;
 using InstARM32Vneg = InstARM32UnaryopSignAwareFP<InstARM32::Vneg>;
 using InstARM32Vorr = InstARM32ThreeAddrFP<InstARM32::Vorr>;
 using InstARM32Vshl = InstARM32ThreeAddrSignAwareFP<InstARM32::Vshl>;
+using InstARM32Vshr = InstARM32ThreeAddrSignAwareFP<InstARM32::Vshr>;
 using InstARM32Vsub = InstARM32ThreeAddrFP<InstARM32::Vsub>;
 using InstARM32Ldr = InstARM32LoadBase<InstARM32::Ldr>;
 using InstARM32Ldrex = InstARM32LoadBase<InstARM32::Ldrex>;
 /// MovT leaves the bottom bits alone so dest is also a source. This helps
 /// indicate that a previous MovW setting dest is not dead code.
 using InstARM32Movt = InstARM32TwoAddrGPR<InstARM32::Movt>;
 using InstARM32Movw = InstARM32UnaryopGPR<InstARM32::Movw, false>;
 using InstARM32Clz = InstARM32UnaryopGPR<InstARM32::Clz, false>;
 using InstARM32Mvn = InstARM32UnaryopGPR<InstARM32::Mvn, false>;
 using InstARM32Rbit = InstARM32UnaryopGPR<InstARM32::Rbit, false>;
@@ skipping 345 matching lines @@
   Variable *DestHi;
 };
 
 /// Handles fp2int, int2fp, and fp2fp conversions.
 class InstARM32Vcvt final : public InstARM32Pred {
   InstARM32Vcvt() = delete;
   InstARM32Vcvt(const InstARM32Vcvt &) = delete;
   InstARM32Vcvt &operator=(const InstARM32Vcvt &) = delete;
 
 public:
-  enum VcvtVariant { S2si, S2ui, Si2s, Ui2s, D2si, D2ui, Si2d, Ui2d, S2d, D2s };
+  enum VcvtVariant {
+    S2si,
+    S2ui,
+    Si2s,
+    Ui2s,
+    D2si,
+    D2ui,
+    Si2d,
+    Ui2d,
+    S2d,
+    D2s,
+    Vs2si,
+    Vs2ui,
+    Vsi2s,
+    Vui2s,
+  };
   static InstARM32Vcvt *create(Cfg *Func, Variable *Dest, Variable *Src,
                                VcvtVariant Variant, CondARM32::Cond Predicate) {
     return new (Func->allocate<InstARM32Vcvt>())
         InstARM32Vcvt(Func, Dest, Src, Variant, Predicate);
   }
   void emit(const Cfg *Func) const override;
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Instr) { return isClassof(Instr, Vcvt); }
 
@@ skipping 212 matching lines @@
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H