Subzero. ARM32. Vector casts.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 817 matching lines @@
   case IceType_v8i1:
   case IceType_v16i1:
   case IceType_v16i8:
   case IceType_v8i16:
   case IceType_v4i32: {
     const Type ElmtTy = typeElementType(DestTy);
     assert(Sign != InstARM32::FS_None);
     switch (Sign) {
     case InstARM32::FS_None: // defaults to unsigned.
     case InstARM32::FS_Unsigned:
-      Asm->vshlqu(ElmtTy, Dest, getSrc(0), getSrc(1));
+      if (const auto *Imm6 = llvm::dyn_cast<ConstantInteger32>(getSrc(1))) {
+        Asm->vshlqc(ElmtTy, Dest, getSrc(0), Imm6);
+      } else {
+        Asm->vshlqu(ElmtTy, Dest, getSrc(0), getSrc(1));
+      }
       break;
     case InstARM32::FS_Signed:
-      Asm->vshlqi(ElmtTy, Dest, getSrc(0), getSrc(1));
+      if (const auto *Imm6 = llvm::dyn_cast<ConstantInteger32>(getSrc(1))) {
+        Asm->vshlqc(ElmtTy, Dest, getSrc(0), Imm6);
+      } else {
+        Asm->vshlqi(ElmtTy, Dest, getSrc(0), getSrc(1));
+      }
       break;
     }
   } break;
+  }
+}
+
+template <> void InstARM32Vshr::emitIAS(const Cfg *Func) const {
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  const Variable *Dest = getDest();
+  const Type DestTy = Dest->getType();
+  switch (DestTy) {
+  default:
+    llvm::report_fatal_error("Vshr not defined on type " +
+                             typeStdString(Dest->getType()));
+  case IceType_v4i1:
+  case IceType_v8i1:
+  case IceType_v16i1:
+  case IceType_v16i8:
+  case IceType_v8i16:
+  case IceType_v4i32: {
+    const Type ElmtTy = typeElementType(DestTy);
+    const auto *Imm6 = llvm::cast<ConstantInteger32>(getSrc(1));
+    assert(Sign != InstARM32::FS_None);
+    switch (Sign) {
+    case InstARM32::FS_None: // defaults to unsigned.
+    case InstARM32::FS_Unsigned:
+      Asm->vshrquc(ElmtTy, Dest, getSrc(0), Imm6);
+      break;
+    case InstARM32::FS_Signed:
+      Asm->vshrqic(ElmtTy, Dest, getSrc(0), Imm6);
+      break;
+    }
+  } break;
   }
 }
 
 template <> void InstARM32Vsub::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Variable *Dest = getDest();
   Type DestTy = Dest->getType();
   switch (DestTy) {
   default:
     llvm::report_fatal_error("Vsub not defined on type " +
@@ skipping 604 matching lines @@
 template <> const char *InstARM32Vadd::Opcode = "vadd";
 template <> const char *InstARM32Vand::Opcode = "vand";
 template <> const char *InstARM32Vdiv::Opcode = "vdiv";
 template <> const char *InstARM32Veor::Opcode = "veor";
 template <> const char *InstARM32Vmla::Opcode = "vmla";
 template <> const char *InstARM32Vmls::Opcode = "vmls";
 template <> const char *InstARM32Vmul::Opcode = "vmul";
 template <> const char *InstARM32Vorr::Opcode = "vorr";
 template <> const char *InstARM32UnaryopFP<InstARM32::Vneg>::Opcode = "vneg";
 template <> const char *InstARM32ThreeAddrFP<InstARM32::Vshl>::Opcode = "vshl";
+template <> const char *InstARM32ThreeAddrFP<InstARM32::Vshr>::Opcode = "vshr";
 template <> const char *InstARM32Vsub::Opcode = "vsub";
 // Four-addr ops
 template <> const char *InstARM32Mla::Opcode = "mla";
 template <> const char *InstARM32Mls::Opcode = "mls";
 // Cmp-like ops
 template <> const char *InstARM32Cmn::Opcode = "cmn";
 template <> const char *InstARM32Cmp::Opcode = "cmp";
 template <> const char *InstARM32Tst::Opcode = "tst";
 
 void InstARM32::dump(const Cfg *Func) const {
@@ skipping 966 matching lines @@
   case InstARM32Vcvt::D2ui:
     return ".u32.f64";
   case InstARM32Vcvt::Si2d:
     return ".f64.s32";
   case InstARM32Vcvt::Ui2d:
     return ".f64.u32";
   case InstARM32Vcvt::S2d:
     return ".f64.f32";
   case InstARM32Vcvt::D2s:
     return ".f32.f64";
+  case InstARM32Vcvt::Vs2si:
+    return ".s32.f32";
+  case InstARM32Vcvt::Vs2ui:
+    return ".u32.f32";
+  case InstARM32Vcvt::Vsi2s:
+    return ".f32.s32";
+  case InstARM32Vcvt::Vui2s:
+    return ".f32.u32";
   }
   llvm::report_fatal_error("Invalid VcvtVariant enum.");
 }
 } // end of anonymous namespace
 
 void InstARM32Vcvt::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
@@ skipping 31 matching lines @@
     break;
   case Ui2d:
     Asm->vcvtdu(getDest(), getSrc(0), getPredicate());
     break;
   case S2d:
     Asm->vcvtds(getDest(), getSrc(0), getPredicate());
     break;
   case D2s:
     Asm->vcvtsd(getDest(), getSrc(0), getPredicate());
     break;
+  case Vs2si:
+    Asm->vcvtqsi(getDest(), getSrc(0));
+    break;
+  case Vs2ui:
+    Asm->vcvtqsu(getDest(), getSrc(0));
+    break;
+  case Vsi2s:
+    Asm->vcvtqis(getDest(), getSrc(0));
+    break;
+  case Vui2s:
+    Asm->vcvtqus(getDest(), getSrc(0));
+    break;
   }
   assert(!Asm->needsTextFixup());
 }
 
 void InstARM32Vcvt::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   dumpDest(Func);
   Str << " = "
@@ skipping 390 matching lines @@
 template class InstARM32ThreeAddrGPR<InstARM32::Udiv>;
 
 template class InstARM32ThreeAddrFP<InstARM32::Vadd>;
 template class InstARM32ThreeAddrFP<InstARM32::Vdiv>;
 template class InstARM32ThreeAddrFP<InstARM32::Veor>;
 template class InstARM32FourAddrFP<InstARM32::Vmla>;
 template class InstARM32FourAddrFP<InstARM32::Vmls>;
 template class InstARM32ThreeAddrFP<InstARM32::Vmul>;
 template class InstARM32UnaryopSignAwareFP<InstARM32::Vneg>;
 template class InstARM32ThreeAddrSignAwareFP<InstARM32::Vshl>;
+template class InstARM32ThreeAddrSignAwareFP<InstARM32::Vshr>;
 template class InstARM32ThreeAddrFP<InstARM32::Vsub>;
 
 template class InstARM32LoadBase<InstARM32::Ldr>;
 template class InstARM32LoadBase<InstARM32::Ldrex>;
 
 template class InstARM32TwoAddrGPR<InstARM32::Movt>;
 
 template class InstARM32UnaryopGPR<InstARM32::Movw, false>;
 template class InstARM32UnaryopGPR<InstARM32::Clz, false>;
 template class InstARM32UnaryopGPR<InstARM32::Mvn, false>;
 template class InstARM32UnaryopGPR<InstARM32::Rbit, false>;
 template class InstARM32UnaryopGPR<InstARM32::Rev, false>;
 template class InstARM32UnaryopGPR<InstARM32::Sxt, true>;
 template class InstARM32UnaryopGPR<InstARM32::Uxt, true>;
 template class InstARM32UnaryopFP<InstARM32::Vsqrt>;
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice