Subzero. ARM32. Vector casts.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 363 matching lines @@
 
   // vcvt<c>.F32.U32
   void vcvtsu(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond);
 
   // vcvt<c>.U32.F64
   void vcvtud(const Operand *OpSd, const Operand *OpDm, CondARM32::Cond Cond);
 
   // vcvt<c>.u32.f32
   void vcvtus(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond);
 
+  void vcvtqsi(const Operand *OpQd, const Operand *OpQm);
+
+  void vcvtqsu(const Operand *OpQd, const Operand *OpQm);
+
+  void vcvtqis(const Operand *OpQd, const Operand *OpQm);
+
+  void vcvtqus(const Operand *OpQd, const Operand *OpQm);
+
   void vdivd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
              CondARM32::Cond Cond);
 
   void vdivs(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
              CondARM32::Cond Cond);
 
   void veord(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm);
 
   void veorq(const Operand *OpQd, const Operand *OpQn, const Operand *OpQm);
 
@@ skipping 110 matching lines @@
 
   void vpush(const Variable *OpBaseReg, SizeT NumConsecRegs,
              CondARM32::Cond Cond);
 
   void vshlqi(Type ElmtTy, const Operand *OpQd, const Operand *OpQm,
               const Operand *OpQn);
 
   void vshlqu(Type ElmtTy, const Operand *OpQd, const Operand *OpQm,
               const Operand *OpQn);
 
+  void vshlqc(Type ElmtTy, const Operand *OpQd, const Operand *OpQm,
+              const ConstantInteger32 *OpQn);
+
+  void vshrqic(Type ElmtTy, const Operand *OpQd, const Operand *OpQm,
+               const ConstantInteger32 *OpQn);
+
+  void vshrquc(Type ElmtTy, const Operand *OpQd, const Operand *OpQm,
+               const ConstantInteger32 *OpQn);
+
   void vsqrtd(const Operand *OpDd, const Operand *OpDm, CondARM32::Cond Cond);
 
   void vsqrts(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond Cond);
 
   void vstrd(const Operand *OpDd, const Operand *OpAddress,
              CondARM32::Cond Cond, const TargetInfo &TInfo);
 
   void vstrd(const Operand *OpDd, const Operand *OpAddress,
              CondARM32::Cond Cond, const TargetLowering *Lowering) {
     const TargetInfo TInfo(Lowering);
@@ skipping 208 matching lines @@
   void emitSIMDqqqBase(IValueT Opcode, const Operand *OpQd, const Operand *OpQn,
                        const Operand *OpQm, bool IsFloatTy,
                        const char *OpcodeName);
 
   // Same as emitSIMD above, except ElmtShift=20 and ElmtSize is computed from
   // ElmtTy.
   void emitSIMDqqq(IValueT Opcode, Type ElmtTy, const Operand *OpQd,
                    const Operand *OpQn, const Operand *OpQm,
                    const char *OpcodeName);
 
+  // Implements various forms of vector (SIMD) shifts using Q registers.
+  // Implements pattern 111100101Diiiiiidddd010101M1mmmm where Dddd=Qd, Mmmm=Qm,
+  // iiiiii=Imm6, and Opcode is unioned into the pattern.
+  void emitSIMDShiftqqc(IValueT Opcode, const Operand *OpQd,
+                        const Operand *OpQm, const IValueT Imm6,
+                        const char *OpcodeName);
+
+  // Implements various forms of vector (SIMD) casts between (signed and
+  // unsigned) integer and floating point types (f32). Implements pattern
+  // 111100111D11ss11dddd011ooQM0mmmm where Dddd=Qd, Mmmm=Qm, 10=ss, op=00, 1=Q,
+  // and Opcode is unioned into the pattern.
+  void emitSIMDCvtqq(IValueT Opcode, const Operand *OpQd, const Operand *OpQm,
+                     const char *CvtName);
+
   // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn,
   // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from
   // OpSrc1, and xxxx=Opcode.
   void emitCompareOp(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpRn,
                      const Operand *OpSrc1, const char *CmpName);
 
   void emitBranch(Label *L, CondARM32::Cond, bool Link);
 
   // Returns the offset encoded in the branch instruction Inst.
   static IOffsetT decodeBranchOffset(IValueT Inst);
@@ skipping 18 matching lines @@
 
   void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd,
                   const Operand *OpSn, const Operand *OpSm,
                   const char *InstName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H