Subzero. ARM32. Vector casts.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 206 matching lines @@
 
 // Figures out Op/Cmode values for given Value. Returns true if able to encode.
 bool encodeAdvSIMDExpandImm(IValueT Value, Type ElmtTy, IValueT &Op,
                             IValueT &Cmode, IValueT &Imm8) {
   // TODO(kschimpf): Handle other shifted 8-bit values.
   constexpr IValueT Imm8Mask = 0xFF;
   if ((Value & IValueT(~Imm8Mask)) != 0)
     return false;
   Imm8 = Value;
   switch (ElmtTy) {
+  case IceType_i8:
+    Op = 0;
+    Cmode = 14; // 0b1110
+    return true;
   case IceType_i16:
     Op = 0;
-    Cmode = 8; // 100:0
+    Cmode = 8; // 0b1000
     return true;
   case IceType_i32:
     Op = 0;
-    Cmode = 0; // 000:0
+    Cmode = 0; // 0b0000
     return true;
   default:
     return false;
   }
 }
 
 // Defines layouts of an operand representing a (register) memory address,
 // possibly modified by an immediate value.
 enum EncodedImmAddress {
   // Address modified by a rotated immediate 8-bit value.
@@ skipping 964 matching lines @@
 void AssemblerARM32::emitSIMDqqq(IValueT Opcode, Type ElmtTy,
                                  const Operand *OpQd, const Operand *OpQn,
                                  const Operand *OpQm, const char *OpcodeName) {
   constexpr IValueT ElmtShift = 20;
   const IValueT ElmtSize = encodeElmtType(ElmtTy);
   assert(Utils::IsUint(2, ElmtSize));
   emitSIMDqqqBase(Opcode | (ElmtSize << ElmtShift), OpQd, OpQn, OpQm,
                   isFloatingType(ElmtTy), OpcodeName);
 }
 
+void AssemblerARM32::emitSIMDShiftqqc(IValueT Opcode, const Operand *OpQd,
+                                      const Operand *OpQm, const IValueT Imm6,
+                                      const char *OpcodeName) {
+  const IValueT Qd = encodeQRegister(OpQd, "Qd", OpcodeName);
+  const IValueT Qn = 0;
+  const IValueT Qm = encodeQRegister(OpQm, "Qm", OpcodeName);
+  constexpr bool UseQRegs = true;
+  constexpr bool IsFloatTy = false;
+  constexpr IValueT ElmtShift = 16;
+  emitSIMDBase(Opcode | (Imm6 << ElmtShift), mapQRegToDReg(Qd),
+               mapQRegToDReg(Qn), mapQRegToDReg(Qm), UseQRegs, IsFloatTy);
+}
+
+void AssemblerARM32::emitSIMDCvtqq(IValueT Opcode, const Operand *OpQd,
+                                   const Operand *OpQm,
+                                   const char *OpcodeName) {
+  const IValueT SIMDOpcode =
+      B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B9 | Opcode;
+  constexpr bool UseQRegs = true;
+  constexpr bool IsFloatTy = false;
+  const IValueT Qd = encodeQRegister(OpQd, "Qd", OpcodeName);
+  constexpr IValueT Qn = 0;
+  const IValueT Qm = encodeQRegister(OpQm, "Qm", OpcodeName);
+  emitSIMDBase(SIMDOpcode, mapQRegToDReg(Qd), mapQRegToDReg(Qn),
+               mapQRegToDReg(Qm), UseQRegs, IsFloatTy);
+}
+
 void AssemblerARM32::emitVFPddd(CondARM32::Cond Cond, IValueT Opcode,
                                 IValueT Dd, IValueT Dn, IValueT Dm) {
   assert(Dd < RegARM32::getNumDRegs());
   assert(Dn < RegARM32::getNumDRegs());
   assert(Dm < RegARM32::getNumDRegs());
   assert(CondARM32::isDefined(Cond));
   constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9 | B8;
   const IValueT Encoding =
       Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
@@ skipping 1322 matching lines @@
   //
   // cccc11101D111100dddd10011M0mmmm where cccc=Cond, ddddD=Sd, and mmmmM=Sm.
   constexpr const char *Vcvtus = "vcvtus";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vcvtus);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vcvtus);
   constexpr IValueT VcvtsiOpcode = B23 | B21 | B20 | B19 | B18 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VcvtsiOpcode, Sd, S0, Sm);
 }
 
+void AssemblerARM32::vcvtqsi(const Operand *OpQd, const Operand *OpQm) {
+  // VCVT (between floating-point and integer, Advanced SIMD)
+  //      - ARM Section A8.8.305, encoding A1:
+  //   vcvt<c>.f32.s32 <Qd>, <Qm>
+  //
+  // 111100111D11ss11dddd011ooQM0mmmm where Ddddd=Qd, Mmmmm=Qm, and 10=op.
+  constexpr const char *Vcvtqsi = "vcvt.s32.f32";
+  constexpr IValueT VcvtqsiOpcode = B8;
+  emitSIMDCvtqq(VcvtqsiOpcode, OpQd, OpQm, Vcvtqsi);
+}
+
+void AssemblerARM32::vcvtqsu(const Operand *OpQd, const Operand *OpQm) {
+  // VCVT (between floating-point and integer, Advanced SIMD)
+  //      - ARM Section A8.8.305, encoding A1:
+  //   vcvt<c>.f32.u32 <Qd>, <Qm>
+  //
+  // 111100111D11ss11dddd011ooQM0mmmm where Ddddd=Qd, Mmmmm=Qm, and 11=op.
+  constexpr const char *Vcvtqsu = "vcvt.u32.f32";
+  constexpr IValueT VcvtqsuOpcode = B8 | B7;
+  emitSIMDCvtqq(VcvtqsuOpcode, OpQd, OpQm, Vcvtqsu);
+}
+
+void AssemblerARM32::vcvtqis(const Operand *OpQd, const Operand *OpQm) {
+  // VCVT (between floating-point and integer, Advanced SIMD)
+  //      - ARM Section A8.8.305, encoding A1:
+  //   vcvt<c>.f32.s32 <Qd>, <Qm>
+  //
+  // 111100111D11ss11dddd011ooQM0mmmm where Ddddd=Qd, Mmmmm=Qm, and 01=op.
+  constexpr const char *Vcvtqis = "vcvt.f32.s32";
+  constexpr IValueT VcvtqisOpcode = 0;
+  emitSIMDCvtqq(VcvtqisOpcode, OpQd, OpQm, Vcvtqis);
+}
+
+void AssemblerARM32::vcvtqus(const Operand *OpQd, const Operand *OpQm) {
+  // VCVT (between floating-point and integer, Advanced SIMD)
+  //      - ARM Section A8.8.305, encoding A1:
+  //   vcvt<c>.f32.u32 <Qd>, <Qm>
+  //
+  // 111100111D11ss11dddd011ooQM0mmmm where Ddddd=Qd, Mmmmm=Qm, and 01=op.
+  constexpr const char *Vcvtqus = "vcvt.f32.u32";
+  constexpr IValueT VcvtqusOpcode = B7;
+  emitSIMDCvtqq(VcvtqusOpcode, OpQd, OpQm, Vcvtqus);
+}
+
 void AssemblerARM32::emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd,
                                IValueT Sm) {
   assert(Dd < RegARM32::getNumDRegs());
   assert(Sm < RegARM32::getNumSRegs());
   assert(CondARM32::isDefined(Cond));
   constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9;
   const IValueT Encoding =
       Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dd) << 12) |
       (getYInRegXXXXY(Sm) << 5) | getXXXXInRegXXXXY(Sm);
@@ skipping 690 matching lines @@
   //
   // 1111001U0Dssnnnndddd0100NQM0mmmm where Ddddd=Qd, Mmmmm=Qm, Nnnnn=Qn, 0=U,
   // 1=Q
   assert(isScalarIntegerType(ElmtTy) &&
          "vshl expects vector with integer element type");
   constexpr const char *Vshl = "vshl";
   constexpr IValueT VshlOpcode = B10 | B6;
   emitSIMDqqq(VshlOpcode, ElmtTy, OpQd, OpQn, OpQm, Vshl);
 }
 
+namespace {
+enum SIMDShiftType { ST_Vshl, ST_Vshr };
+IValueT encodeSIMDShiftImm6(SIMDShiftType Shift, Type ElmtTy,
+                            const ConstantInteger32 *Imm6) {
+  const IValueT Imm = Imm6->getValue();
+  assert(Imm > 0);
+  const SizeT MaxShift = getScalarIntBitWidth(ElmtTy);
+  assert(Imm < MaxShift);
+  assert(ElmtTy == IceType_i8 || ElmtTy == IceType_i16 ||
+         ElmtTy == IceType_i32);
+  const IValueT VshlImm = Imm - MaxShift;
+  const IValueT VshrImm = 2 * MaxShift - Imm;
+  return ((Shift == ST_Vshl) ? VshlImm : VshrImm) & (2 * MaxShift - 1);
+}
+} // end of anonymous namespace
+
+void AssemblerARM32::vshlqc(Type ElmtTy, const Operand *OpQd,
+                            const Operand *OpQm,
+                            const ConstantInteger32 *Imm6) {
+  // VSHL - ARM section A8.8.395, encoding A1:
+  //   vshl Qd, Qm, #Imm
+  //
+  // 1111001U1Diiiiiidddd0101LQM1mmmm where Ddddd=Qd, Mmmmm=Qm, iiiiii=Imm6,
+  // 0=U, 1=Q, 0=L.
+  assert(isScalarIntegerType(ElmtTy) &&
+         "vshl expects vector with integer element type");
+  constexpr const char *Vshl = "vshl";
+  constexpr IValueT VshlOpcode = B23 | B10 | B8 | B4;
+  emitSIMDShiftqqc(VshlOpcode, OpQd, OpQm,
+                   encodeSIMDShiftImm6(ST_Vshl, ElmtTy, Imm6), Vshl);
+}
+
+void AssemblerARM32::vshrqic(Type ElmtTy, const Operand *OpQd,
+                             const Operand *OpQm,
+                             const ConstantInteger32 *Imm6) {
+  // VSHR - ARM section A8.8.398, encoding A1:
+  //   vshr Qd, Qm, #Imm
+  //
+  // 1111001U1Diiiiiidddd0101LQM1mmmm where Ddddd=Qd, Mmmmm=Qm, iiiiii=Imm6,
+  // 0=U, 1=Q, 0=L.
+  assert(isScalarIntegerType(ElmtTy) &&
+         "vshr expects vector with integer element type");
+  constexpr const char *Vshr = "vshr";
+  constexpr IValueT VshrOpcode = B23 | B4;
+  emitSIMDShiftqqc(VshrOpcode, OpQd, OpQm,
+                   encodeSIMDShiftImm6(ST_Vshr, ElmtTy, Imm6), Vshr);
+}
+
+void AssemblerARM32::vshrquc(Type ElmtTy, const Operand *OpQd,
+                             const Operand *OpQm,
+                             const ConstantInteger32 *Imm6) {
+  // VSHR - ARM section A8.8.398, encoding A1:
+  //   vshr Qd, Qm, #Imm
+  //
+  // 1111001U1Diiiiiidddd0101LQM1mmmm where Ddddd=Qd, Mmmmm=Qm, iiiiii=Imm6,
+  // 0=U, 1=Q, 0=L.
+  assert(isScalarIntegerType(ElmtTy) &&
+         "vshr expects vector with integer element type");
+  constexpr const char *Vshr = "vshr";
+  constexpr IValueT VshrOpcode = B23 | B4;
+  emitSIMDShiftqqc(VshrOpcode, OpQd, OpQm,
+                   encodeSIMDShiftImm6(ST_Vshr, ElmtTy, Imm6), Vshr);
+}
+
 void AssemblerARM32::vshlqu(Type ElmtTy, const Operand *OpQd,
                             const Operand *OpQm, const Operand *OpQn) {
   // VSHL - ARM section A8.8.396, encoding A1:
   //   vshl Qd, Qm, Qn
   //
   // 1111001U0Dssnnnndddd0100NQM0mmmm where Ddddd=Qd, Mmmmm=Qm, Nnnnn=Qn, 1=U,
   // 1=Q
   assert(isScalarIntegerType(ElmtTy) &&
          "vshl expects vector with integer element type");
   constexpr const char *Vshl = "vshl";
@@ skipping 24 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice