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Issue 18773003: ARM: Add support for temp double registers in Crankshaft. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 7 years, 5 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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75 case LUnallocated::FIXED_DOUBLE_REGISTER: { 75 case LUnallocated::FIXED_DOUBLE_REGISTER: {
76 int reg_index = unalloc->fixed_register_index(); 76 int reg_index = unalloc->fixed_register_index();
77 const char* double_register_name = 77 const char* double_register_name =
78 DoubleRegister::AllocationIndexToString(reg_index); 78 DoubleRegister::AllocationIndexToString(reg_index);
79 stream->Add("(=%s)", double_register_name); 79 stream->Add("(=%s)", double_register_name);
80 break; 80 break;
81 } 81 }
82 case LUnallocated::MUST_HAVE_REGISTER: 82 case LUnallocated::MUST_HAVE_REGISTER:
83 stream->Add("(R)"); 83 stream->Add("(R)");
84 break; 84 break;
85 case LUnallocated::TEMP_DOUBLE_REGISTER:
86 stream->Add("(D)");
87 break;
85 case LUnallocated::WRITABLE_REGISTER: 88 case LUnallocated::WRITABLE_REGISTER:
86 stream->Add("(WR)"); 89 stream->Add("(WR)");
87 break; 90 break;
88 case LUnallocated::SAME_AS_FIRST_INPUT: 91 case LUnallocated::SAME_AS_FIRST_INPUT:
89 stream->Add("(1)"); 92 stream->Add("(1)");
90 break; 93 break;
91 case LUnallocated::ANY: 94 case LUnallocated::ANY:
92 stream->Add("(-)"); 95 stream->Add("(-)");
93 break; 96 break;
94 } 97 }
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493 496
494 497
495 LPhase::~LPhase() { 498 LPhase::~LPhase() {
496 if (ShouldProduceTraceOutput()) { 499 if (ShouldProduceTraceOutput()) {
497 isolate()->GetHTracer()->TraceLithium(name(), chunk_); 500 isolate()->GetHTracer()->TraceLithium(name(), chunk_);
498 } 501 }
499 } 502 }
500 503
501 504
502 } } // namespace v8::internal 505 } } // namespace v8::internal
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