| OLD | NEW |
| 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
| (...skipping 260 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 271 /// end up writing to memory. Operation also needs to handle fake-defing for | 271 /// end up writing to memory. Operation also needs to handle fake-defing for |
| 272 /// i64 handling. | 272 /// i64 handling. |
| 273 void | 273 void |
| 274 lowerLoadLinkedStoreExclusive(Type Ty, Operand *Addr, | 274 lowerLoadLinkedStoreExclusive(Type Ty, Operand *Addr, |
| 275 std::function<Variable *(Variable *)> Operation, | 275 std::function<Variable *(Variable *)> Operation, |
| 276 CondARM32::Cond Cond = CondARM32::AL); | 276 CondARM32::Cond Cond = CondARM32::AL); |
| 277 void lowerInt64AtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr, | 277 void lowerInt64AtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr, |
| 278 Operand *Val); | 278 Operand *Val); |
| 279 void lowerAtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr, | 279 void lowerAtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr, |
| 280 Operand *Val); | 280 Operand *Val); |
| 281 void lowerBreakpoint(const InstBreakpoint *Instr) override; |
| 281 void lowerIntrinsicCall(const InstIntrinsicCall *Instr) override; | 282 void lowerIntrinsicCall(const InstIntrinsicCall *Instr) override; |
| 282 void lowerInsertElement(const InstInsertElement *Instr) override; | 283 void lowerInsertElement(const InstInsertElement *Instr) override; |
| 283 void lowerLoad(const InstLoad *Instr) override; | 284 void lowerLoad(const InstLoad *Instr) override; |
| 284 void lowerPhi(const InstPhi *Instr) override; | 285 void lowerPhi(const InstPhi *Instr) override; |
| 285 void lowerRet(const InstRet *Instr) override; | 286 void lowerRet(const InstRet *Instr) override; |
| 286 void lowerSelect(const InstSelect *Instr) override; | 287 void lowerSelect(const InstSelect *Instr) override; |
| 287 void lowerStore(const InstStore *Instr) override; | 288 void lowerStore(const InstStore *Instr) override; |
| 288 void lowerSwitch(const InstSwitch *Instr) override; | 289 void lowerSwitch(const InstSwitch *Instr) override; |
| 289 void lowerUnreachable(const InstUnreachable *Instr) override; | 290 void lowerUnreachable(const InstUnreachable *Instr) override; |
| 290 void prelowerPhis() override; | 291 void prelowerPhis() override; |
| (...skipping 1059 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1350 private: | 1351 private: |
| 1351 ~TargetHeaderARM32() = default; | 1352 ~TargetHeaderARM32() = default; |
| 1352 | 1353 |
| 1353 TargetARM32Features CPUFeatures; | 1354 TargetARM32Features CPUFeatures; |
| 1354 }; | 1355 }; |
| 1355 | 1356 |
| 1356 } // end of namespace ARM32 | 1357 } // end of namespace ARM32 |
| 1357 } // end of namespace Ice | 1358 } // end of namespace Ice |
| 1358 | 1359 |
| 1359 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 1360 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
| OLD | NEW |