Subzero. WASM. Additional progress.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 5791 matching lines @@
 
   for (SizeT I = 0; I < NumCases; ++I) {
     Operand *Value = Ctx->getConstantInt32(Instr->getValue(I) << ShiftAmt);
     Value = legalize(Value, Legal_Reg | Legal_Flex);
     _cmp(Src0Var, Value);
     _br(Instr->getLabel(I), CondARM32::EQ);
   }
   _br(Instr->getLabelDefault());
 }
 
+void TargetARM32::lowerBreakpoint(const InstBreakpoint *Instr) {
+  UnimplementedLoweringError(this, Instr);
+}
+
 void TargetARM32::lowerUnreachable(const InstUnreachable * /*Instr*/) {
   _trap();
 }
 
 namespace {
 // Returns whether Opnd needs the GOT address. Currently, ConstantRelocatables,
 // and fp constants will need access to the GOT address.
 bool operandNeedsGot(const Operand *Opnd) {
   if (llvm::isa<ConstantRelocatable>(Opnd)) {
     return true;
@@ skipping 1163 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice