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Issue 1876083004: Subzero. ARM32. Fixes Insert/Extract v(8|16)i1 bug. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fixes lit. Created 4 years, 8 months ago
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1 ; Test that we handle select on vectors. 1 ; Test that we handle select on vectors.
2 2
3 ; TODO(eholk): This test will need to be updated once comparison is no longer 3 ; TODO(eholk): This test will need to be updated once comparison is no longer
4 ; scalarized. 4 ; scalarized.
5 5
6 ; REQUIRES: allow_dump 6 ; REQUIRES: allow_dump
7 7
8 ; Compile using standalone assembler. 8 ; Compile using standalone assembler.
9 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ 9 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
10 ; RUN: | FileCheck %s --check-prefix=ASM 10 ; RUN: | FileCheck %s --check-prefix=ASM
11 11
12 define internal <4 x float> @select4float(<4 x i1> %s, <4 x float> %a, 12 define internal <4 x float> @select4float(<4 x i1> %s, <4 x float> %a,
13 <4 x float> %b) { 13 <4 x float> %b) {
14 ; ASM-LABEL:select4float: 14 ; ASM-LABEL:select4float:
15 ; DIS-LABEL:00000000 <select4float>: 15 ; DIS-LABEL:00000000 <select4float>:
16 16
17 entry: 17 entry:
18 %res = select <4 x i1> %s, <4 x float> %a, <4 x float> %b 18 %res = select <4 x i1> %s, <4 x float> %a, <4 x float> %b
19 19
20 ; ASM: # q3 = def.pseudo 20 ; ASM: # q3 = def.pseudo
21 ; ASM-NEXT: vmov.s8 r0, d0[0] 21 ; ASM-NEXT: vmov.s8 r0, d0[0]
22 ; ASM-NEXT: vmov.f32 s16, s4 22 ; ASM-NEXT: vmov.f32 s16, s4
23 ; ASM-NEXT: vmov.f32 s17, s8 23 ; ASM-NEXT: vmov.f32 s17, s8
24 ; ASM-NEXT: tst r0, #1 24 ; ASM-NEXT: tst r0, #1
25 ; ASM-NEXT: vmovne.f32 s17, s16 25 ; ASM-NEXT: vmovne.f32 s17, s16
26 ; ASM-NEXT: vmov.f32 s12, s17 26 ; ASM-NEXT: vmov.f32 s12, s17
27 ; ASM-NEXT:» vmov.s8»r0, d0[1] 27 ; ASM-NEXT:» vmov.s8»r0, d0[4]
28 ; ASM-NEXT: vmov.f32 s16, s5 28 ; ASM-NEXT: vmov.f32 s16, s5
29 ; ASM-NEXT: vmov.f32 s17, s9 29 ; ASM-NEXT: vmov.f32 s17, s9
30 ; ASM-NEXT: tst r0, #1 30 ; ASM-NEXT: tst r0, #1
31 ; ASM-NEXT: vmovne.f32 s17, s16 31 ; ASM-NEXT: vmovne.f32 s17, s16
32 ; ASM-NEXT: vmov.f32 s13, s17 32 ; ASM-NEXT: vmov.f32 s13, s17
33 ; ASM-NEXT: vmov.s8 r0, d1[0] 33 ; ASM-NEXT: vmov.s8 r0, d1[0]
34 ; ASM-NEXT: vmov.f32 s16, s6 34 ; ASM-NEXT: vmov.f32 s16, s6
35 ; ASM-NEXT: vmov.f32 s17, s10 35 ; ASM-NEXT: vmov.f32 s17, s10
36 ; ASM-NEXT: tst r0, #1 36 ; ASM-NEXT: tst r0, #1
37 ; ASM-NEXT: vmovne.f32 s17, s16 37 ; ASM-NEXT: vmovne.f32 s17, s16
38 ; ASM-NEXT: vmov.f32 s14, s17 38 ; ASM-NEXT: vmov.f32 s14, s17
39 ; ASM-NEXT:» vmov.s8»r0, d1[1] 39 ; ASM-NEXT:» vmov.s8»r0, d1[4]
40 ; ASM-NEXT: vmov.f32 s4, s7 40 ; ASM-NEXT: vmov.f32 s4, s7
41 ; ASM-NEXT: vmov.f32 s8, s11 41 ; ASM-NEXT: vmov.f32 s8, s11
42 ; ASM-NEXT: tst r0, #1 42 ; ASM-NEXT: tst r0, #1
43 ; ASM-NEXT: vmovne.f32 s8, s4 43 ; ASM-NEXT: vmovne.f32 s8, s4
44 ; ASM-NEXT: vmov.f32 s15, s8 44 ; ASM-NEXT: vmov.f32 s15, s8
45 ; ASM-NEXT: vmov.f32 q0, q3 45 ; ASM-NEXT: vmov.f32 q0, q3
46 ; ASM-NEXT: vpop {s16, s17} 46 ; ASM-NEXT: vpop {s16, s17}
47 ; ASM-NEXT: # s16 = def.pseudo 47 ; ASM-NEXT: # s16 = def.pseudo
48 ; ASM-NEXT: # s17 = def.pseudo 48 ; ASM-NEXT: # s17 = def.pseudo
49 ; ASM-NEXT: bx lr 49 ; ASM-NEXT: bx lr
50 50
51 ret <4 x float> %res 51 ret <4 x float> %res
52 } 52 }
53 53
54 define internal <4 x i32> @select4i32(<4 x i1> %s, <4 x i32> %a, <4 x i32> %b) { 54 define internal <4 x i32> @select4i32(<4 x i1> %s, <4 x i32> %a, <4 x i32> %b) {
55 ; ASM-LABEL:select4i32: 55 ; ASM-LABEL:select4i32:
56 ; DIS-LABEL:00000000 <select4i32>: 56 ; DIS-LABEL:00000000 <select4i32>:
57 57
58 entry: 58 entry:
59 %res = select <4 x i1> %s, <4 x i32> %a, <4 x i32> %b 59 %res = select <4 x i1> %s, <4 x i32> %a, <4 x i32> %b
60 60
61 ; ASM: # q3 = def.pseudo 61 ; ASM: # q3 = def.pseudo
62 ; ASM-NEXT: vmov.s8 r0, d0[0] 62 ; ASM-NEXT: vmov.s8 r0, d0[0]
63 ; ASM-NEXT: vmov.32 r1, d2[0] 63 ; ASM-NEXT: vmov.32 r1, d2[0]
64 ; ASM-NEXT: vmov.32 r2, d4[0] 64 ; ASM-NEXT: vmov.32 r2, d4[0]
65 ; ASM-NEXT: tst r0, #1 65 ; ASM-NEXT: tst r0, #1
66 ; ASM-NEXT: movne r2, r1 66 ; ASM-NEXT: movne r2, r1
67 ; ASM-NEXT: vmov.32 d6[0], r2 67 ; ASM-NEXT: vmov.32 d6[0], r2
68 ; ASM-NEXT:» vmov.s8»r0, d0[1] 68 ; ASM-NEXT:» vmov.s8»r0, d0[4]
69 ; ASM-NEXT: vmov.32 r1, d2[1] 69 ; ASM-NEXT: vmov.32 r1, d2[1]
70 ; ASM-NEXT: vmov.32 r2, d4[1] 70 ; ASM-NEXT: vmov.32 r2, d4[1]
71 ; ASM-NEXT: tst r0, #1 71 ; ASM-NEXT: tst r0, #1
72 ; ASM-NEXT: movne r2, r1 72 ; ASM-NEXT: movne r2, r1
73 ; ASM-NEXT: vmov.32 d6[1], r2 73 ; ASM-NEXT: vmov.32 d6[1], r2
74 ; ASM-NEXT: vmov.s8 r0, d1[0] 74 ; ASM-NEXT: vmov.s8 r0, d1[0]
75 ; ASM-NEXT: vmov.32 r1, d3[0] 75 ; ASM-NEXT: vmov.32 r1, d3[0]
76 ; ASM-NEXT: vmov.32 r2, d5[0] 76 ; ASM-NEXT: vmov.32 r2, d5[0]
77 ; ASM-NEXT: tst r0, #1 77 ; ASM-NEXT: tst r0, #1
78 ; ASM-NEXT: movne r2, r1 78 ; ASM-NEXT: movne r2, r1
79 ; ASM-NEXT: vmov.32 d7[0], r2 79 ; ASM-NEXT: vmov.32 d7[0], r2
80 ; ASM-NEXT:» vmov.s8»r0, d1[1] 80 ; ASM-NEXT:» vmov.s8»r0, d1[4]
81 ; ASM-NEXT: vmov.32 r1, d3[1] 81 ; ASM-NEXT: vmov.32 r1, d3[1]
82 ; ASM-NEXT: vmov.32 r2, d5[1] 82 ; ASM-NEXT: vmov.32 r2, d5[1]
83 ; ASM-NEXT: tst r0, #1 83 ; ASM-NEXT: tst r0, #1
84 ; ASM-NEXT: movne r2, r1 84 ; ASM-NEXT: movne r2, r1
85 ; ASM-NEXT: vmov.32 d7[1], r2 85 ; ASM-NEXT: vmov.32 d7[1], r2
86 ; ASM-NEXT: vmov.i32 q0, q3 86 ; ASM-NEXT: vmov.i32 q0, q3
87 ; ASM-NEXT: bx lr 87 ; ASM-NEXT: bx lr
88 88
89 ret <4 x i32> %res 89 ret <4 x i32> %res
90 } 90 }
91 91
92 define internal <8 x i16> @select8i16(<8 x i1> %s, <8 x i16> %a, <8 x i16> %b) { 92 define internal <8 x i16> @select8i16(<8 x i1> %s, <8 x i16> %a, <8 x i16> %b) {
93 ; ASM-LABEL:select8i16: 93 ; ASM-LABEL:select8i16:
94 ; DIS-LABEL:00000000 <select8i16>: 94 ; DIS-LABEL:00000000 <select8i16>:
95 95
96 entry: 96 entry:
97 %res = select <8 x i1> %s, <8 x i16> %a, <8 x i16> %b 97 %res = select <8 x i1> %s, <8 x i16> %a, <8 x i16> %b
98 98
99 ; ASM: # q3 = def.pseudo 99 ; ASM: # q3 = def.pseudo
100 ; ASM-NEXT: vmov.s8 r0, d0[0] 100 ; ASM-NEXT: vmov.s8 r0, d0[0]
101 ; ASM-NEXT: vmov.s16 r1, d2[0] 101 ; ASM-NEXT: vmov.s16 r1, d2[0]
102 ; ASM-NEXT: vmov.s16 r2, d4[0] 102 ; ASM-NEXT: vmov.s16 r2, d4[0]
103 ; ASM-NEXT: tst r0, #1 103 ; ASM-NEXT: tst r0, #1
104 ; ASM-NEXT: movne r2, r1 104 ; ASM-NEXT: movne r2, r1
105 ; ASM-NEXT: vmov.16 d6[0], r2 105 ; ASM-NEXT: vmov.16 d6[0], r2
106 ; ASM-NEXT:» vmov.s8»r0, d0[1] 106 ; ASM-NEXT:» vmov.s8»r0, d0[2]
107 ; ASM-NEXT: vmov.s16 r1, d2[1] 107 ; ASM-NEXT: vmov.s16 r1, d2[1]
108 ; ASM-NEXT: vmov.s16 r2, d4[1] 108 ; ASM-NEXT: vmov.s16 r2, d4[1]
109 ; ASM-NEXT: tst r0, #1 109 ; ASM-NEXT: tst r0, #1
110 ; ASM-NEXT: movne r2, r1 110 ; ASM-NEXT: movne r2, r1
111 ; ASM-NEXT: vmov.16 d6[1], r2 111 ; ASM-NEXT: vmov.16 d6[1], r2
112 ; ASM-NEXT:» vmov.s8»r0, d0[2] 112 ; ASM-NEXT:» vmov.s8»r0, d0[4]
113 ; ASM-NEXT: vmov.s16 r1, d2[2] 113 ; ASM-NEXT: vmov.s16 r1, d2[2]
114 ; ASM-NEXT: vmov.s16 r2, d4[2] 114 ; ASM-NEXT: vmov.s16 r2, d4[2]
115 ; ASM-NEXT: tst r0, #1 115 ; ASM-NEXT: tst r0, #1
116 ; ASM-NEXT: movne r2, r1 116 ; ASM-NEXT: movne r2, r1
117 ; ASM-NEXT: vmov.16 d6[2], r2 117 ; ASM-NEXT: vmov.16 d6[2], r2
118 ; ASM-NEXT:» vmov.s8»r0, d0[3] 118 ; ASM-NEXT:» vmov.s8»r0, d0[6]
119 ; ASM-NEXT: vmov.s16 r1, d2[3] 119 ; ASM-NEXT: vmov.s16 r1, d2[3]
120 ; ASM-NEXT: vmov.s16 r2, d4[3] 120 ; ASM-NEXT: vmov.s16 r2, d4[3]
121 ; ASM-NEXT: tst r0, #1 121 ; ASM-NEXT: tst r0, #1
122 ; ASM-NEXT: movne r2, r1 122 ; ASM-NEXT: movne r2, r1
123 ; ASM-NEXT: vmov.16 d6[3], r2 123 ; ASM-NEXT: vmov.16 d6[3], r2
124 ; ASM-NEXT: vmov.s8 r0, d1[0] 124 ; ASM-NEXT: vmov.s8 r0, d1[0]
125 ; ASM-NEXT: vmov.s16 r1, d3[0] 125 ; ASM-NEXT: vmov.s16 r1, d3[0]
126 ; ASM-NEXT: vmov.s16 r2, d5[0] 126 ; ASM-NEXT: vmov.s16 r2, d5[0]
127 ; ASM-NEXT: tst r0, #1 127 ; ASM-NEXT: tst r0, #1
128 ; ASM-NEXT: movne r2, r1 128 ; ASM-NEXT: movne r2, r1
129 ; ASM-NEXT: vmov.16 d7[0], r2 129 ; ASM-NEXT: vmov.16 d7[0], r2
130 ; ASM-NEXT:» vmov.s8»r0, d1[1] 130 ; ASM-NEXT:» vmov.s8»r0, d1[2]
131 ; ASM-NEXT: vmov.s16 r1, d3[1] 131 ; ASM-NEXT: vmov.s16 r1, d3[1]
132 ; ASM-NEXT: vmov.s16 r2, d5[1] 132 ; ASM-NEXT: vmov.s16 r2, d5[1]
133 ; ASM-NEXT: tst r0, #1 133 ; ASM-NEXT: tst r0, #1
134 ; ASM-NEXT: movne r2, r1 134 ; ASM-NEXT: movne r2, r1
135 ; ASM-NEXT: vmov.16 d7[1], r2 135 ; ASM-NEXT: vmov.16 d7[1], r2
136 ; ASM-NEXT:» vmov.s8»r0, d1[2] 136 ; ASM-NEXT:» vmov.s8»r0, d1[4]
137 ; ASM-NEXT: vmov.s16 r1, d3[2] 137 ; ASM-NEXT: vmov.s16 r1, d3[2]
138 ; ASM-NEXT: vmov.s16 r2, d5[2] 138 ; ASM-NEXT: vmov.s16 r2, d5[2]
139 ; ASM-NEXT: tst r0, #1 139 ; ASM-NEXT: tst r0, #1
140 ; ASM-NEXT: movne r2, r1 140 ; ASM-NEXT: movne r2, r1
141 ; ASM-NEXT: vmov.16 d7[2], r2 141 ; ASM-NEXT: vmov.16 d7[2], r2
142 ; ASM-NEXT:» vmov.s8»r0, d1[3] 142 ; ASM-NEXT:» vmov.s8»r0, d1[6]
143 ; ASM-NEXT: vmov.s16 r1, d3[3] 143 ; ASM-NEXT: vmov.s16 r1, d3[3]
144 ; ASM-NEXT: vmov.s16 r2, d5[3] 144 ; ASM-NEXT: vmov.s16 r2, d5[3]
145 ; ASM-NEXT: tst r0, #1 145 ; ASM-NEXT: tst r0, #1
146 ; ASM-NEXT: movne r2, r1 146 ; ASM-NEXT: movne r2, r1
147 ; ASM-NEXT: vmov.16 d7[3], r2 147 ; ASM-NEXT: vmov.16 d7[3], r2
148 ; ASM-NEXT: vmov.i16 q0, q3 148 ; ASM-NEXT: vmov.i16 q0, q3
149 ; ASM-NEXT: bx lr 149 ; ASM-NEXT: bx lr
150 150
151 ret <8 x i16> %res 151 ret <8 x i16> %res
152 } 152 }
(...skipping 101 matching lines...) Expand 10 before | Expand all | Expand 10 after
254 ; ASM-NEXT: vmov.s8 r1, d3[7] 254 ; ASM-NEXT: vmov.s8 r1, d3[7]
255 ; ASM-NEXT: vmov.s8 r2, d5[7] 255 ; ASM-NEXT: vmov.s8 r2, d5[7]
256 ; ASM-NEXT: tst r0, #1 256 ; ASM-NEXT: tst r0, #1
257 ; ASM-NEXT: movne r2, r1 257 ; ASM-NEXT: movne r2, r1
258 ; ASM-NEXT: vmov.8 d7[7], r2 258 ; ASM-NEXT: vmov.8 d7[7], r2
259 ; ASM-NEXT: vmov.i8 q0, q3 259 ; ASM-NEXT: vmov.i8 q0, q3
260 ; ASM-NEXT: bx lr 260 ; ASM-NEXT: bx lr
261 261
262 ret <16 x i8> %res 262 ret <16 x i8> %res
263 } 263 }
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