Begins implementation of ARM neon instructions.

runtime/vm/flow_graph_compiler_arm.cc

Index: runtime/vm/flow_graph_compiler_arm.cc
===================================================================
--- runtime/vm/flow_graph_compiler_arm.cc	(revision 24916)
+++ runtime/vm/flow_graph_compiler_arm.cc	(working copy)
@@ -1503,9 +1503,12 @@
     // address.
     intptr_t offset = 0;
     for (intptr_t reg_idx = 0; reg_idx < kNumberOfFpuRegisters; ++reg_idx) {
-      DRegister fpu_reg = static_cast<DRegister>(reg_idx);
+      QRegister fpu_reg = static_cast<QRegister>(reg_idx);
       if (locs->live_registers()->ContainsFpuRegister(fpu_reg)) {
-        __ vstrd(fpu_reg, Address(SP, offset));
+        DRegister d1 = static_cast<DRegister>(fpu_reg * 2);
+        DRegister d2 = static_cast<DRegister>(fpu_reg * 2 + 1);

[regis, 2013/07/12 22:16:01]

Use macros

[zra, 2013/07/12 23:22:18]

Done.

+        __ vstrd(d1, Address(SP, offset));
+        __ vstrd(d2, Address(SP, offset + 2 * kWordSize));
         offset += kFpuRegisterSize;
       }
     }
@@ -1536,9 +1539,12 @@
     // Fpu registers have the lowest register number at the lowest address.
     intptr_t offset = 0;
     for (intptr_t reg_idx = 0; reg_idx < kNumberOfFpuRegisters; ++reg_idx) {
-      DRegister fpu_reg = static_cast<DRegister>(reg_idx);
+      QRegister fpu_reg = static_cast<QRegister>(reg_idx);
       if (locs->live_registers()->ContainsFpuRegister(fpu_reg)) {
-        __ vldrd(fpu_reg, Address(SP, offset));
+        DRegister d1 = static_cast<DRegister>(fpu_reg * 2);
+        DRegister d2 = static_cast<DRegister>(fpu_reg * 2 + 1);
+        __ vldrd(d1, Address(SP, offset));
+        __ vldrd(d2, Address(SP, offset + 2 * kWordSize));
         offset += kFpuRegisterSize;
       }
     }
@@ -1601,7 +1607,9 @@
                                                 FpuRegister right,
                                                 BranchInstr* branch) {
   ASSERT(branch != NULL);
-  assembler()->vcmpd(left, right);
+  DRegister dleft = static_cast<DRegister>(left * 2);
+  DRegister dright = static_cast<DRegister>(right * 2);
+  assembler()->vcmpd(dleft, dright);
   assembler()->vmstat();
   BlockEntryInstr* nan_result = (true_condition == NE) ?
       branch->true_successor() : branch->false_successor();
@@ -1614,7 +1622,9 @@
                                               FpuRegister left,
                                               FpuRegister right,
                                               Register result) {
-  assembler()->vcmpd(left, right);
+  DRegister dleft = static_cast<DRegister>(left * 2);
+  DRegister dright = static_cast<DRegister>(right * 2);
+  assembler()->vcmpd(dleft, dright);
   assembler()->vmstat();
   assembler()->LoadObject(result, Bool::False());
   Label done;
@@ -1688,10 +1698,13 @@
     }
   } else if (source.IsFpuRegister()) {
     if (destination.IsFpuRegister()) {
-      __ vmovd(destination.fpu_reg(), source.fpu_reg());
+      DRegister dst = static_cast<DRegister>(destination.fpu_reg() * 2);
+      DRegister src = static_cast<DRegister>(source.fpu_reg() * 2);
+      __ vmovd(dst, src);
     } else {
       if (destination.IsDoubleStackSlot()) {
-        __ vstrd(source.fpu_reg(), destination.ToStackSlotAddress());
+        DRegister src = static_cast<DRegister>(source.fpu_reg() * 2);
+        __ vstrd(src, destination.ToStackSlotAddress());
       } else {
         ASSERT(destination.IsQuadStackSlot());
         UNIMPLEMENTED();
@@ -1699,7 +1712,8 @@
     }
   } else if (source.IsDoubleStackSlot()) {
     if (destination.IsFpuRegister()) {
-      __ vldrd(destination.fpu_reg(), source.ToStackSlotAddress());
+      DRegister dst = static_cast<DRegister>(destination.fpu_reg() * 2);
+      __ vldrd(dst, source.ToStackSlotAddress());
     } else {
       ASSERT(destination.IsDoubleStackSlot());
       __ vldrd(DTMP, source.ToStackSlotAddress());
@@ -1740,9 +1754,11 @@
   } else if (source.IsStackSlot() && destination.IsStackSlot()) {
     Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress());
   } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
-    __ vmovd(DTMP, source.fpu_reg());
-    __ vmovd(source.fpu_reg(), destination.fpu_reg());
-    __ vmovd(destination.fpu_reg(), DTMP);
+    DRegister dst = static_cast<DRegister>(destination.fpu_reg() * 2);
+    DRegister src = static_cast<DRegister>(source.fpu_reg() * 2);
+    __ vmovd(DTMP, src);
+    __ vmovd(src, dst);
+    __ vmovd(dst, DTMP);
   } else if (source.IsFpuRegister() || destination.IsFpuRegister()) {
     ASSERT(destination.IsDoubleStackSlot() ||
            destination.IsQuadStackSlot() ||
@@ -1750,8 +1766,9 @@
            source.IsQuadStackSlot());
     bool double_width = destination.IsDoubleStackSlot() ||
                         source.IsDoubleStackSlot();
-    DRegister reg = source.IsFpuRegister() ? source.fpu_reg()
-                                           : destination.fpu_reg();
+    QRegister qreg = source.IsFpuRegister() ? source.fpu_reg()
+                                            : destination.fpu_reg();
+    DRegister reg = static_cast<DRegister>(qreg * 2);
     const Address& slot_address = source.IsFpuRegister()
         ? destination.ToStackSlotAddress()
         : source.ToStackSlotAddress();
@@ -1767,11 +1784,12 @@
     const Address& source_slot_address = source.ToStackSlotAddress();
     const Address& destination_slot_address = destination.ToStackSlotAddress();
 
-    ScratchFpuRegisterScope ensure_scratch(this, DTMP);
+    ScratchFpuRegisterScope ensure_scratch(this, QTMP);
+    DRegister scratch = static_cast<DRegister>(ensure_scratch.reg() * 2);
     __ vldrd(DTMP, source_slot_address);
-    __ vldrd(ensure_scratch.reg(), destination_slot_address);
+    __ vldrd(scratch, destination_slot_address);
     __ vstrd(DTMP, destination_slot_address);
-    __ vstrd(ensure_scratch.reg(), source_slot_address);
+    __ vstrd(scratch, source_slot_address);
   } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) {
     UNIMPLEMENTED();
   } else {
@@ -1837,12 +1855,14 @@
 
 
 void ParallelMoveResolver::SpillFpuScratch(FpuRegister reg) {
-  __ vstrd(reg, Address(SP, -kDoubleSize, Address::PreIndex));
+  DRegister dreg = static_cast<DRegister>(reg * 2);
+  __ vstrd(dreg, Address(SP, -kDoubleSize, Address::PreIndex));
 }
 
 
 void ParallelMoveResolver::RestoreFpuScratch(FpuRegister reg) {
-  __ vldrd(reg, Address(SP, kDoubleSize, Address::PostIndex));
+  DRegister dreg = static_cast<DRegister>(reg * 2);
+  __ vldrd(dreg, Address(SP, kDoubleSize, Address::PostIndex));
 }