Begins implementation of ARM neon instructions.

runtime/vm/assembler_arm.h

Index: runtime/vm/assembler_arm.h
===================================================================
--- runtime/vm/assembler_arm.h	(revision 24916)
+++ runtime/vm/assembler_arm.h	(working copy)
@@ -68,11 +68,14 @@
   static void InitOnce();
   static bool double_truncate_round_supported() { return false; }
   static bool integer_division_supported();
+  static bool neon_supported();
 #if defined(USING_SIMULATOR)
   static void set_integer_division_supported(bool supported);
+  static void set_neon_supported(bool supported);
 #endif
  private:
   static bool integer_division_supported_;
+  static bool neon_supported_;
 #if defined(DEBUG)
   static bool initialized_;
 #endif
@@ -476,6 +479,8 @@
 
   void vadds(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
   void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
+  void vaddi(int sz, QRegister qd, QRegister qn, QRegister qm);

[regis, 2013/07/12 22:16:01]

I think this would be a good time to merge the enums LoadOperandType and
StoreOperandType to a single OperandSize enum:
  kByte,
  kUnsignedByte,
  kHalfword,
  kUnsignedHalfword,
  kWord,
  kUnsignedWord,   <-- new
  kWordPair,
  kSWord,
  kDWord,

Then, how about splitting this instruction in two:
vaddqi(OperandSize sz, QRegister qd, QRegister qn, QRegister qm)
vadddi(OperandSize sz, DRegister dd, DRegister dn, DRegister dm)

[zra, 2013/07/12 23:22:18]

I'll tackle this in my next CL.
Sounds reasonable. Changed. (I'll add the vadddi in a subsequent change.)

+  void vaddf(QRegister qd, QRegister qn, QRegister qm);

[regis, 2013/07/12 22:16:01]

How about
void vaddqs(QRegister qd, QRegister qn, QRegister qm);
and
void vaddds(DRegister dd, DRegister dn, DRegister dm);

VADDL and VADDW would be:
void vaddql(OperandSize sz, QRegister qd, DRegister dn, DRegister dm);
void vaddqw(OperandSize sz, QRegister qd, QRegister qn, DRegister dm);

[zra, 2013/07/12 23:22:18]

Done.
sgtm.

   void vsubs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
   void vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
   void vmuls(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL);
@@ -804,6 +809,9 @@
                  DRegister dd,
                  SRegister sm);
 
+  void EmitSIMDqqq(int32_t opcode, int sz,
+                   QRegister qd, QRegister qn, QRegister qm);
+
   void EmitBranch(Condition cond, Label* label, bool link);
   static int32_t EncodeBranchOffset(int32_t offset, int32_t inst);
   static int DecodeBranchOffset(int32_t inst);