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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 | 4 |
5 #include <math.h> // for isnan. | 5 #include <math.h> // for isnan. |
6 #include <setjmp.h> | 6 #include <setjmp.h> |
7 #include <stdlib.h> | 7 #include <stdlib.h> |
8 | 8 |
9 #include "vm/globals.h" | 9 #include "vm/globals.h" |
10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
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916 dregisters_[reg] = bit_cast<int64_t, double>(value); | 916 dregisters_[reg] = bit_cast<int64_t, double>(value); |
917 } | 917 } |
918 | 918 |
919 | 919 |
920 double Simulator::get_dregister(DRegister reg) const { | 920 double Simulator::get_dregister(DRegister reg) const { |
921 ASSERT((reg >= 0) && (reg < kNumberOfDRegisters)); | 921 ASSERT((reg >= 0) && (reg < kNumberOfDRegisters)); |
922 return bit_cast<double, int64_t>(dregisters_[reg]); | 922 return bit_cast<double, int64_t>(dregisters_[reg]); |
923 } | 923 } |
924 | 924 |
925 | 925 |
| 926 void Simulator::set_qregister(QRegister reg, simd_value_t value) { |
| 927 ASSERT((reg >= 0) && (reg < kNumberOfQRegisters)); |
| 928 qregisters_[reg].data_[0] = value.data_[0]; |
| 929 qregisters_[reg].data_[1] = value.data_[1]; |
| 930 qregisters_[reg].data_[2] = value.data_[2]; |
| 931 qregisters_[reg].data_[3] = value.data_[3]; |
| 932 } |
| 933 |
| 934 |
| 935 simd_value_t Simulator::get_qregister(QRegister reg) const { |
| 936 ASSERT((reg >= 0) && (reg < kNumberOfQRegisters)); |
| 937 return qregisters_[reg]; |
| 938 } |
| 939 |
| 940 |
926 void Simulator::set_sregister_bits(SRegister reg, int32_t value) { | 941 void Simulator::set_sregister_bits(SRegister reg, int32_t value) { |
927 ASSERT((reg >= 0) && (reg < kNumberOfSRegisters)); | 942 ASSERT((reg >= 0) && (reg < kNumberOfSRegisters)); |
928 sregisters_[reg] = value; | 943 sregisters_[reg] = value; |
929 } | 944 } |
930 | 945 |
931 | 946 |
932 int32_t Simulator::get_sregister_bits(SRegister reg) const { | 947 int32_t Simulator::get_sregister_bits(SRegister reg) const { |
933 ASSERT((reg >= 0) && (reg < kNumberOfSRegisters)); | 948 ASSERT((reg >= 0) && (reg < kNumberOfSRegisters)); |
934 return sregisters_[reg]; | 949 return sregisters_[reg]; |
935 } | 950 } |
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2877 } else { | 2892 } else { |
2878 UnimplementedInstruction(instr); | 2893 UnimplementedInstruction(instr); |
2879 } | 2894 } |
2880 } | 2895 } |
2881 } else { | 2896 } else { |
2882 UnimplementedInstruction(instr); | 2897 UnimplementedInstruction(instr); |
2883 } | 2898 } |
2884 } | 2899 } |
2885 | 2900 |
2886 | 2901 |
| 2902 void Simulator::DecodeSIMDDataProcessing(Instr* instr) { |
| 2903 ASSERT(instr->ConditionField() == kSpecialCondition); |
| 2904 |
| 2905 if (instr->Bit(6) == 1) { |
| 2906 // Q = 1, Using 128-bit Q registers. |
| 2907 const QRegister qd = instr->QdField(); |
| 2908 const QRegister qn = instr->QnField(); |
| 2909 const QRegister qm = instr->QmField(); |
| 2910 simd_value_t s8d; |
| 2911 simd_value_t s8n = get_qregister(qn); |
| 2912 simd_value_t s8m = get_qregister(qm); |
| 2913 int8_t* s8d_8 = reinterpret_cast<int8_t*>(&s8d); |
| 2914 int8_t* s8n_8 = reinterpret_cast<int8_t*>(&s8n); |
| 2915 int8_t* s8m_8 = reinterpret_cast<int8_t*>(&s8m); |
| 2916 int16_t* s8d_16 = reinterpret_cast<int16_t*>(&s8d); |
| 2917 int16_t* s8n_16 = reinterpret_cast<int16_t*>(&s8n); |
| 2918 int16_t* s8m_16 = reinterpret_cast<int16_t*>(&s8m); |
| 2919 int64_t* s8d_64 = reinterpret_cast<int64_t*>(&s8d); |
| 2920 int64_t* s8n_64 = reinterpret_cast<int64_t*>(&s8n); |
| 2921 int64_t* s8m_64 = reinterpret_cast<int64_t*>(&s8m); |
| 2922 |
| 2923 if ((instr->Bits(8, 4) == 8) && (instr->Bit(4) == 0) && |
| 2924 (instr->Bit(24) == 0)) { |
| 2925 // Uses q registers. |
| 2926 // Format(instr, "vadd.'sz 'qd, 'qn, 'qm"); |
| 2927 const int size = instr->Bits(20, 2); |
| 2928 if (size == 0) { |
| 2929 for (int i = 0; i < 16; i++) { |
| 2930 s8d_8[i] = s8n_8[i] + s8m_8[i]; |
| 2931 } |
| 2932 } else if (size == 1) { |
| 2933 for (int i = 0; i < 8; i++) { |
| 2934 s8d_16[i] = s8n_16[i] + s8m_16[i]; |
| 2935 } |
| 2936 } else if (size == 2) { |
| 2937 for (int i = 0; i < 4; i++) { |
| 2938 s8d.data_[i].u = s8n.data_[i].u + s8m.data_[i].u; |
| 2939 } |
| 2940 } else if (size == 3) { |
| 2941 for (int i = 0; i < 2; i++) { |
| 2942 s8d_64[i] = s8n_64[i] + s8m_64[i]; |
| 2943 } |
| 2944 } else { |
| 2945 UNREACHABLE(); |
| 2946 } |
| 2947 } else if ((instr->Bits(8, 4) == 13) && (instr->Bit(4) == 0) && |
| 2948 (instr->Bit(24) == 0)) { |
| 2949 // Format(instr, "vadd.F32 'qd, 'qn, 'qm"); |
| 2950 for (int i = 0; i < 4; i++) { |
| 2951 s8d.data_[i].f = s8n.data_[i].f + s8m.data_[i].f; |
| 2952 } |
| 2953 } else { |
| 2954 UnimplementedInstruction(instr); |
| 2955 } |
| 2956 |
| 2957 set_qregister(qd, s8d); |
| 2958 } else { |
| 2959 // Q == 0, Uses 64-bit D registers. |
| 2960 UnimplementedInstruction(instr); |
| 2961 } |
| 2962 } |
| 2963 |
| 2964 |
2887 // Executes the current instruction. | 2965 // Executes the current instruction. |
2888 void Simulator::InstructionDecode(Instr* instr) { | 2966 void Simulator::InstructionDecode(Instr* instr) { |
2889 pc_modified_ = false; | 2967 pc_modified_ = false; |
2890 if (FLAG_trace_sim) { | 2968 if (FLAG_trace_sim) { |
2891 const uword start = reinterpret_cast<uword>(instr); | 2969 const uword start = reinterpret_cast<uword>(instr); |
2892 const uword end = start + Instr::kInstrSize; | 2970 const uword end = start + Instr::kInstrSize; |
2893 Disassembler::Disassemble(start, end); | 2971 Disassembler::Disassemble(start, end); |
2894 } | 2972 } |
2895 if (instr->ConditionField() == kSpecialCondition) { | 2973 if (instr->ConditionField() == kSpecialCondition) { |
2896 if (instr->InstructionBits() == static_cast<int32_t>(0xf57ff01f)) { | 2974 if (instr->InstructionBits() == static_cast<int32_t>(0xf57ff01f)) { |
2897 // Format(instr, "clrex"); | 2975 // Format(instr, "clrex"); |
2898 ClearExclusive(); | 2976 ClearExclusive(); |
2899 } else { | 2977 } else { |
2900 UnimplementedInstruction(instr); | 2978 if (instr->IsSIMDDataProcessing()) { |
| 2979 DecodeSIMDDataProcessing(instr); |
| 2980 } else { |
| 2981 UnimplementedInstruction(instr); |
| 2982 } |
2901 } | 2983 } |
2902 } else if (ConditionallyExecute(instr)) { | 2984 } else if (ConditionallyExecute(instr)) { |
2903 switch (instr->TypeField()) { | 2985 switch (instr->TypeField()) { |
2904 case 0: | 2986 case 0: |
2905 case 1: { | 2987 case 1: { |
2906 DecodeType01(instr); | 2988 DecodeType01(instr); |
2907 break; | 2989 break; |
2908 } | 2990 } |
2909 case 2: { | 2991 case 2: { |
2910 DecodeType2(instr); | 2992 DecodeType2(instr); |
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3114 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception)); | 3196 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception)); |
3115 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace)); | 3197 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace)); |
3116 buf->Longjmp(); | 3198 buf->Longjmp(); |
3117 } | 3199 } |
3118 | 3200 |
3119 } // namespace dart | 3201 } // namespace dart |
3120 | 3202 |
3121 #endif // !defined(HOST_ARCH_ARM) | 3203 #endif // !defined(HOST_ARCH_ARM) |
3122 | 3204 |
3123 #endif // defined TARGET_ARCH_ARM | 3205 #endif // defined TARGET_ARCH_ARM |
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