Begins implementation of ARM neon instructions.

runtime/vm/flow_graph_compiler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/flow_graph_compiler.h"
 
 #include "lib/error.h"
@@ skipping 1489 matching lines @@
 
 void FlowGraphCompiler::SaveLiveRegisters(LocationSummary* locs) {
   // TODO(vegorov): consider saving only caller save (volatile) registers.
   const intptr_t fpu_regs_count = locs->live_registers()->fpu_regs_count();
   if (fpu_regs_count > 0) {
     __ AddImmediate(SP, -(fpu_regs_count * kFpuRegisterSize));
     // Store fpu registers with the lowest register number at the lowest
     // address.
     intptr_t offset = 0;
     for (intptr_t reg_idx = 0; reg_idx < kNumberOfFpuRegisters; ++reg_idx) {
-      DRegister fpu_reg = static_cast<DRegister>(reg_idx);
+      QRegister fpu_reg = static_cast<QRegister>(reg_idx);
       if (locs->live_registers()->ContainsFpuRegister(fpu_reg)) {
-        __ vstrd(fpu_reg, Address(SP, offset));
+        DRegister d1 = EvenDRegisterOf(fpu_reg);
+        DRegister d2 = OddDRegisterOf(fpu_reg);
+        __ vstrd(d1, Address(SP, offset));
+        __ vstrd(d2, Address(SP, offset + 2 * kWordSize));

[regis, 2013/07/16 00:18:42]

Fine for now, but you should add a TODO (my name is fine :-) to make use of the
vstm instruction that could save some code.

         offset += kFpuRegisterSize;
       }
     }
     ASSERT(offset == (fpu_regs_count * kFpuRegisterSize));
   }
 
   // Store general purpose registers with the lowest register number at the
   // lowest address.
   const intptr_t cpu_registers = locs->live_registers()->cpu_registers();
   ASSERT((cpu_registers & ~kAllCpuRegistersList) == 0);
@@ skipping 10 matching lines @@
   ASSERT((cpu_registers & ~kAllCpuRegistersList) == 0);
   if (cpu_registers != 0) {
     __ PopList(cpu_registers);
   }
 
   const intptr_t fpu_regs_count = locs->live_registers()->fpu_regs_count();
   if (fpu_regs_count > 0) {
     // Fpu registers have the lowest register number at the lowest address.
     intptr_t offset = 0;
     for (intptr_t reg_idx = 0; reg_idx < kNumberOfFpuRegisters; ++reg_idx) {
-      DRegister fpu_reg = static_cast<DRegister>(reg_idx);
+      QRegister fpu_reg = static_cast<QRegister>(reg_idx);
       if (locs->live_registers()->ContainsFpuRegister(fpu_reg)) {
-        __ vldrd(fpu_reg, Address(SP, offset));
+        DRegister d1 = EvenDRegisterOf(fpu_reg);
+        DRegister d2 = OddDRegisterOf(fpu_reg);
+        __ vldrd(d1, Address(SP, offset));
+        __ vldrd(d2, Address(SP, offset + 2 * kWordSize));

[regis, 2013/07/16 00:18:42]

TODO(regis): Use vldm instruction.

         offset += kFpuRegisterSize;
       }
     }
     ASSERT(offset == (fpu_regs_count * kFpuRegisterSize));
     __ AddImmediate(SP, offset);
   }
 }
 
 
 void FlowGraphCompiler::EmitTestAndCall(const ICData& ic_data,
@@ skipping 42 matching lines @@
   }
   assembler()->Bind(&match_found);
 }
 
 
 void FlowGraphCompiler::EmitDoubleCompareBranch(Condition true_condition,
                                                 FpuRegister left,
                                                 FpuRegister right,
                                                 BranchInstr* branch) {
   ASSERT(branch != NULL);
-  assembler()->vcmpd(left, right);
+  DRegister dleft = EvenDRegisterOf(left);
+  DRegister dright = EvenDRegisterOf(right);
+  assembler()->vcmpd(dleft, dright);
   assembler()->vmstat();
   BlockEntryInstr* nan_result = (true_condition == NE) ?
       branch->true_successor() : branch->false_successor();
   assembler()->b(GetJumpLabel(nan_result), VS);
   branch->EmitBranchOnCondition(this, true_condition);
 }
 
 
 void FlowGraphCompiler::EmitDoubleCompareBool(Condition true_condition,
                                               FpuRegister left,
                                               FpuRegister right,
                                               Register result) {
-  assembler()->vcmpd(left, right);
+  DRegister dleft = EvenDRegisterOf(left);
+  DRegister dright = EvenDRegisterOf(right);
+  assembler()->vcmpd(dleft, dright);
   assembler()->vmstat();
   assembler()->LoadObject(result, Bool::False());
   Label done;
   assembler()->b(&done, VS);  // NaN -> false.
   assembler()->LoadObject(result, Bool::True(), true_condition);
   assembler()->Bind(&done);
 }
 
 
 // Do not implement or use this function.
@@ skipping 53 matching lines @@
   } else if (source.IsStackSlot()) {
     if (destination.IsRegister()) {
       __ ldr(destination.reg(), source.ToStackSlotAddress());
     } else {
       ASSERT(destination.IsStackSlot());
       MoveMemoryToMemory(destination.ToStackSlotAddress(),
                          source.ToStackSlotAddress());
     }
   } else if (source.IsFpuRegister()) {
     if (destination.IsFpuRegister()) {
-      __ vmovd(destination.fpu_reg(), source.fpu_reg());
+      DRegister dst = EvenDRegisterOf(destination.fpu_reg());
+      DRegister src = EvenDRegisterOf(source.fpu_reg());
+      __ vmovd(dst, src);
     } else {
       if (destination.IsDoubleStackSlot()) {
-        __ vstrd(source.fpu_reg(), destination.ToStackSlotAddress());
+        DRegister src = EvenDRegisterOf(source.fpu_reg());
+        __ vstrd(src, destination.ToStackSlotAddress());
       } else {
         ASSERT(destination.IsQuadStackSlot());
         UNIMPLEMENTED();
       }
     }
   } else if (source.IsDoubleStackSlot()) {
     if (destination.IsFpuRegister()) {
-      __ vldrd(destination.fpu_reg(), source.ToStackSlotAddress());
+      DRegister dst = EvenDRegisterOf(destination.fpu_reg());
+      __ vldrd(dst, source.ToStackSlotAddress());
     } else {
       ASSERT(destination.IsDoubleStackSlot());
       __ vldrd(DTMP, source.ToStackSlotAddress());
       __ vstrd(DTMP, destination.ToStackSlotAddress());
     }
   } else if (source.IsQuadStackSlot()) {
     UNIMPLEMENTED();
   } else {
     ASSERT(source.IsConstant());
     if (destination.IsRegister()) {
@@ skipping 20 matching lines @@
     __ mov(IP, ShifterOperand(source.reg()));
     __ mov(source.reg(), ShifterOperand(destination.reg()));
     __ mov(destination.reg(), ShifterOperand(IP));
   } else if (source.IsRegister() && destination.IsStackSlot()) {
     Exchange(source.reg(), destination.ToStackSlotAddress());
   } else if (source.IsStackSlot() && destination.IsRegister()) {
     Exchange(destination.reg(), source.ToStackSlotAddress());
   } else if (source.IsStackSlot() && destination.IsStackSlot()) {
     Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress());
   } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
-    __ vmovd(DTMP, source.fpu_reg());
-    __ vmovd(source.fpu_reg(), destination.fpu_reg());
-    __ vmovd(destination.fpu_reg(), DTMP);
+    DRegister dst = EvenDRegisterOf(destination.fpu_reg());
+    DRegister src = EvenDRegisterOf(source.fpu_reg());
+    __ vmovd(DTMP, src);
+    __ vmovd(src, dst);
+    __ vmovd(dst, DTMP);
   } else if (source.IsFpuRegister() || destination.IsFpuRegister()) {
     ASSERT(destination.IsDoubleStackSlot() ||
            destination.IsQuadStackSlot() ||
            source.IsDoubleStackSlot() ||
            source.IsQuadStackSlot());
     bool double_width = destination.IsDoubleStackSlot() ||
                         source.IsDoubleStackSlot();
-    DRegister reg = source.IsFpuRegister() ? source.fpu_reg()
-                                           : destination.fpu_reg();
+    QRegister qreg = source.IsFpuRegister() ? source.fpu_reg()
+                                            : destination.fpu_reg();
+    DRegister reg = EvenDRegisterOf(qreg);
     const Address& slot_address = source.IsFpuRegister()
         ? destination.ToStackSlotAddress()
         : source.ToStackSlotAddress();
 
     if (double_width) {
       __ vldrd(DTMP, slot_address);
       __ vstrd(reg, slot_address);
       __ vmovd(reg, DTMP);
     } else {
       UNIMPLEMENTED();
     }
   } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) {
     const Address& source_slot_address = source.ToStackSlotAddress();
     const Address& destination_slot_address = destination.ToStackSlotAddress();
 
-    ScratchFpuRegisterScope ensure_scratch(this, DTMP);
+    ScratchFpuRegisterScope ensure_scratch(this, QTMP);
+    DRegister scratch = EvenDRegisterOf(ensure_scratch.reg());
     __ vldrd(DTMP, source_slot_address);
-    __ vldrd(ensure_scratch.reg(), destination_slot_address);
+    __ vldrd(scratch, destination_slot_address);
     __ vstrd(DTMP, destination_slot_address);
-    __ vstrd(ensure_scratch.reg(), source_slot_address);
+    __ vstrd(scratch, source_slot_address);
   } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) {
     UNIMPLEMENTED();
   } else {
     UNREACHABLE();
   }
 
   // The swap of source and destination has executed a move from source to
   // destination.
   move->Eliminate();
 
@@ skipping 45 matching lines @@
   __ Push(reg);
 }
 
 
 void ParallelMoveResolver::RestoreScratch(Register reg) {
   __ Pop(reg);
 }
 
 
 void ParallelMoveResolver::SpillFpuScratch(FpuRegister reg) {
-  __ vstrd(reg, Address(SP, -kDoubleSize, Address::PreIndex));
+  DRegister dreg = EvenDRegisterOf(reg);
+  __ vstrd(dreg, Address(SP, -kDoubleSize, Address::PreIndex));
 }
 
 
 void ParallelMoveResolver::RestoreFpuScratch(FpuRegister reg) {
-  __ vldrd(reg, Address(SP, kDoubleSize, Address::PostIndex));
+  DRegister dreg = EvenDRegisterOf(reg);
+  __ vldrd(dreg, Address(SP, kDoubleSize, Address::PostIndex));
 }
 
 
 #undef __
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM