Begins implementation of ARM neon instructions.

runtime/vm/constants_arm.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_ARM_H_
 #define VM_CONSTANTS_ARM_H_
 
 #include "platform/assert.h"
 
 namespace dart {
@@ skipping 111 matching lines @@
   D29 = 29,
   D30 = 30,
   D31 = 31,
   kNumberOfDRegisters = 32,
 #endif
   kNumberOfOverlappingDRegisters = 16,
   kNoDRegister = -1,
 };
 
 
+enum QRegister {
+  Q0  =  0,
+  Q1  =  1,
+  Q2  =  2,
+  Q3  =  3,
+  Q4  =  4,
+  Q5  =  5,
+  Q6  =  6,
+  Q7  =  7,
+#ifdef VFPv3_D16
+  kNumberOfQRegisters = 8,
+#else
+  Q8  =  8,
+  Q9  =  9,
+  Q10 = 10,
+  Q11 = 11,
+  Q12 = 12,
+  Q13 = 13,
+  Q14 = 14,
+  Q15 = 15,
+  kNumberOfQRegisters = 16,
+#endif
+  kNoQRegister = -1,
+};
+
+
+static inline DRegister EvenDRegisterOf(QRegister q) {
+  return static_cast<DRegister>(q * 2);
+}
+
+static inline DRegister OddDRegisterOf(QRegister q) {
+  return static_cast<DRegister>((q * 2) + 1);
+}
+
+
 // Register aliases for floating point scratch registers.
-const DRegister DTMP = D15;  // Overlaps with STMP.
-const SRegister STMP = S30;
+const QRegister QTMP = Q7;  // Overlaps with DTMP, STMP.
+const DRegister DTMP = D14;  // Overlaps with STMP.
+const SRegister STMP = S28;
 
 // Architecture independent aliases.
-typedef DRegister FpuRegister;
-const FpuRegister FpuTMP = DTMP;
-const int kNumberOfFpuRegisters = kNumberOfDRegisters;
-const FpuRegister kNoFpuRegister = kNoDRegister;
+typedef QRegister FpuRegister;
+const FpuRegister FpuTMP = QTMP;
+const int kNumberOfFpuRegisters = kNumberOfQRegisters;
+const FpuRegister kNoFpuRegister = kNoQRegister;
 
 // Register aliases.
 const Register TMP = IP;  // Used as scratch register by assembler.
 const Register CTX = R9;  // Caches current context in generated code.
 const Register PP = R10;  // Caches object pool pointer in generated code.
 const Register SPREG = SP;  // Stack pointer register.
 const Register FPREG = FP;  // Frame pointer register.
 
 // Exception object is passed in this register to the catch handlers when an
 // exception is thrown.
 const Register kExceptionObjectReg = R0;
 
 // Stack trace object is passed in this register to the catch handlers when
 // an exception is thrown.
 const Register kStackTraceObjectReg = R1;
 
 
 // List of registers used in load/store multiple.
 typedef uint16_t RegList;
 const RegList kAllCpuRegistersList = 0xFFFF;
 
 
 // C++ ABI call registers.
 const RegList kAbiArgumentCpuRegs =
     (1 << R0) | (1 << R1) | (1 << R2) | (1 << R3);
 const RegList kAbiPreservedCpuRegs =
     (1 << R4) | (1 << R5) | (1 << R6) | (1 << R7) |
     (1 << R8) | (1 << R9) | (1 << R10);
 const int kAbiPreservedCpuRegCount = 7;
-const DRegister kAbiFirstPreservedFpuReg = D8;
-const DRegister kAbiLastPreservedFpuReg =
-    static_cast<DRegister>(kNumberOfDRegisters - 1);
+const QRegister kAbiFirstPreservedFpuReg = Q4;
+const QRegister kAbiLastPreservedFpuReg =
+    static_cast<QRegister>(kNumberOfQRegisters - 1);
 
 // CPU registers available to Dart allocator.
 const RegList kDartAvailableCpuRegs =
     (1 << R0) | (1 << R1) | (1 << R2) | (1 << R3) |
     (1 << R4) | (1 << R5) | (1 << R6) | (1 << R7) | (1 << R8);
 
 // Registers available to Dart that are not preserved by runtime calls.
 const RegList kDartVolatileCpuRegs =
     kDartAvailableCpuRegs & ~kAbiPreservedCpuRegs;
 const int kDartVolatileCpuRegCount = 4;
-const DRegister kDartFirstVolatileFpuReg = D0;
-const DRegister kDartLastVolatileFpuReg = D7;
-const int kDartVolatileFpuRegCount = 8;
+const QRegister kDartFirstVolatileFpuReg = Q0;
+const QRegister kDartLastVolatileFpuReg = Q3;
+const int kDartVolatileFpuRegCount = 4;
 
 
 // Values for the condition field as defined in section A3.2.
 enum Condition {
   kNoCondition = -1,
   EQ =  0,  // equal
   NE =  1,  // not equal
   CS =  2,  // carry set/unsigned higher or same
   CC =  3,  // carry clear/unsigned lower
   MI =  4,  // minus/negative
@@ skipping 322 matching lines @@
   }
   inline DRegister DnField() const {
     return static_cast<DRegister>(Bits(kRnShift, kRnBits) + (Bit(7) << 4));
   }
   inline DRegister DdField() const {
     return static_cast<DRegister>(Bits(kRdShift, kRdBits) + (Bit(22) << 4));
   }
   inline DRegister DmField() const {
     return static_cast<DRegister>(Bits(kRmShift, kRmBits) + (Bit(5) << 4));
   }
+  inline QRegister QnField() const {
+    const intptr_t bits = Bits(kRnShift, kRnBits) + (Bit(7) << 4);
+    return static_cast<QRegister>(bits >> 1);
+  }
+  inline QRegister QdField() const {
+    const intptr_t bits = Bits(kRdShift, kRdBits) + (Bit(22) << 4);
+    return static_cast<QRegister>(bits >> 1);
+  }
+  inline QRegister QmField() const {
+    const intptr_t bits = Bits(kRmShift, kRmBits) + (Bit(5) << 4);
+    return static_cast<QRegister>(bits >> 1);
+  }
 
   inline bool IsDivision() const {
     ASSERT(ConditionField() != kSpecialCondition);
     ASSERT(TypeField() == 3);
     return ((Bit(4) == 1) && (Bits(5, 3) == 0) &&
             (Bit(20) == 1) && (Bits(22, 3) == 4));
   }
 
   // Test for VFP data processing or single transfer instructions of type 7.
   inline bool IsVFPDataProcessingOrSingleTransfer() const {
@@ skipping 20 matching lines @@
   }
 
   // Test for VFP multiple load and store instructions of type 6.
   inline bool IsVFPMultipleLoadStore() const {
     ASSERT(ConditionField() != kSpecialCondition);
     ASSERT(TypeField() == 6);
     int32_t puw = (PUField() << 1) | Bit(21);  // don't care about D bit
     return (Bits(9, 3) == 5) && ((puw == 2) || (puw == 3) || (puw == 5));
   }
 
+  inline bool IsSIMDDataProcessing() const {
+    ASSERT(ConditionField() == kSpecialCondition);
+    return (Bits(25, 3) == 1);
+  }
+
+  inline bool IsSIMDLoadStore() const {
+    ASSERT(ConditionField() == kSpecialCondition);
+    return (Bits(24, 4) == 4) && (Bit(20) == 0);
+  }
+
   // Special accessors that test for existence of a value.
   inline bool HasS()    const { return SField() == 1; }
   inline bool HasB()    const { return BField() == 1; }
   inline bool HasW()    const { return WField() == 1; }
   inline bool HasL()    const { return LField() == 1; }
   inline bool HasSign() const { return SignField() == 1; }
   inline bool HasH()    const { return HField() == 1; }
   inline bool HasLink() const { return LinkField() == 1; }
 
   // Instructions are read out of a code stream. The only way to get a
   // reference to an instruction is to convert a pointer. There is no way
   // to allocate or create instances of class Instr.
   // Use the At(pc) function to create references to Instr.
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_ARM_H_