Begins implementation of ARM neon instructions.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/simulator.h"
 #include "vm/runtime_entry.h"
 #include "vm/stack_frame.h"
 #include "vm/stub_code.h"
 
 // An extra check since we are assuming the existence of /proc/cpuinfo below.
 #if !defined(USING_SIMULATOR) && !defined(__linux__)
 #error ARM cross-compile only supported on Linux
 #endif
 
 namespace dart {
 
 DEFINE_FLAG(bool, print_stop_message, true, "Print stop message.");
 DECLARE_FLAG(bool, inline_alloc);
 
 bool CPUFeatures::integer_division_supported_ = false;
+bool CPUFeatures::neon_supported_ = false;
 #if defined(DEBUG)
 bool CPUFeatures::initialized_ = false;
 #endif
 
 
 bool CPUFeatures::integer_division_supported() {
   DEBUG_ASSERT(initialized_);
   return integer_division_supported_;
 }
 
 
+bool CPUFeatures::neon_supported() {
+  DEBUG_ASSERT(initialized_);
+  return neon_supported_;
+}
+
+
 // If we are using the simulator, allow tests to enable/disable support for
 // integer division.
 #if defined(USING_SIMULATOR)
 void CPUFeatures::set_integer_division_supported(bool supported) {
   integer_division_supported_ = supported;
 }
+
+
+void CPUFeatures::set_neon_supported(bool supported) {
+  neon_supported_ = supported;
+}
 #endif
 
 
 // Probe /proc/cpuinfo for features of the ARM processor.
 #if !defined(USING_SIMULATOR)
 static bool CPUInfoContainsString(const char* search_string) {
   const char* file_name = "/proc/cpuinfo";
   // This is written as a straight shot one pass parser
   // and not using STL string and ifstream because,
   // on Linux, it's reading from a (non-mmap-able)
@@ skipping 22 matching lines @@
   fclose(f);
 
   // Did not find string in the proc file.
   return false;
 }
 #endif
 
 void CPUFeatures::InitOnce() {
 #if defined(USING_SIMULATOR)
   integer_division_supported_ = true;
+  neon_supported_ = true;
 #else
   ASSERT(CPUInfoContainsString("ARMv7"));  // Implements ARMv7.
   ASSERT(CPUInfoContainsString("vfp"));  // Has floating point unit.
   // Has integer division.
   integer_division_supported_ = CPUInfoContainsString("idiva");
+  neon_supported_ = CPUInfoContainsString("neon");
 #endif  // defined(USING_SIMULATOR)
 #if defined(DEBUG)
   initialized_ = true;
 #endif
 }
 
 
 // Instruction encoding bits.
 enum {
   H   = 1 << 5,   // halfword (or byte)
@@ skipping 1099 matching lines @@
 void Assembler::vmstat(Condition cond) {  // VMRS APSR_nzcv, FPSCR
   ASSERT(cond != kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 |
                      (static_cast<int32_t>(PC)*B12) |
                      B11 | B9 | B4;
   Emit(encoding);
 }
 
 
+void Assembler::EmitSIMDqqq(int32_t opcode, int sz,
+                            QRegister qd, QRegister qn, QRegister qm) {
+  int32_t encoding =
+      (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
+      B25 | B6 |
+      opcode | ((sz & 0x3) * B20) |
+      ((static_cast<int32_t>(qd * 2) >> 4)*B22) |
+      ((static_cast<int32_t>(qn * 2) & 0xf)*B16) |
+      ((static_cast<int32_t>(qd * 2) & 0xf)*B12) |
+      ((static_cast<int32_t>(qn * 2) >> 4)*B7) |
+      ((static_cast<int32_t>(qm * 2) >> 4)*B5) |
+      (static_cast<int32_t>(qm * 2) & 0xf);
+  Emit(encoding);
+}
+
+
+void Assembler::vaddqi(int sz, QRegister qd, QRegister qn, QRegister qm) {
+  ASSERT((sz >= 0) && (sz <= 3));
+  EmitSIMDqqq(B11, sz, qd, qn, qm);
+}
+
+
+void Assembler::vaddqs(QRegister qd, QRegister qn, QRegister qm) {
+  EmitSIMDqqq(B11 | B10 | B8, 0, qd, qn, qm);
+}
+
+
 void Assembler::svc(uint32_t imm24, Condition cond) {
   ASSERT(cond != kNoCondition);
   ASSERT(imm24 < (1 << 24));
   int32_t encoding = (cond << kConditionShift) | B27 | B26 | B25 | B24 | imm24;
   Emit(encoding);
 }
 
 
 void Assembler::bkpt(uint16_t imm16) {
   // bkpt requires that the cond field is AL.
@@ skipping 792 matching lines @@
     bic(SP, SP, ShifterOperand(OS::ActivationFrameAlignment() - 1));
   }
 }
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
   // Preserve volatile CPU registers.
   EnterFrame(kDartVolatileCpuRegs | (1 << FP) | (1 << LR), 0);
 
   // Preserve all volatile FPU registers.
-  vstmd(DB_W, SP, kDartFirstVolatileFpuReg, kDartLastVolatileFpuReg);
+  DRegister firstv = EvenDRegisterOf(kDartFirstVolatileFpuReg);
+  DRegister lastv = OddDRegisterOf(kDartLastVolatileFpuReg);
+  vstmd(DB_W, SP, firstv, lastv);
 
   ReserveAlignedFrameSpace(frame_space);
 }
 
 
 void Assembler::LeaveCallRuntimeFrame() {
   // SP might have been modified to reserve space for arguments
   // and ensure proper alignment of the stack frame.
   // We need to restore it before restoring registers.
   const intptr_t kPushedRegistersSize =
       kDartVolatileCpuRegCount * kWordSize +
       kDartVolatileFpuRegCount * 2 * kWordSize;
   AddImmediate(SP, FP, -kPushedRegistersSize);
 
   // Restore all volatile FPU registers.
-  vldmd(IA_W, SP, kDartFirstVolatileFpuReg, kDartLastVolatileFpuReg);
+  DRegister firstv = EvenDRegisterOf(kDartFirstVolatileFpuReg);
+  DRegister lastv = OddDRegisterOf(kDartLastVolatileFpuReg);
+  vldmd(IA_W, SP, firstv, lastv);
 
   // Restore volatile CPU registers.
   LeaveFrame(kDartVolatileCpuRegs | (1 << FP) | (1 << LR));
 }
 
 
 void Assembler::CallRuntime(const RuntimeEntry& entry) {
   entry.Call(this);
 }
 
@@ skipping 193 matching lines @@
 };
 
 
 const char* Assembler::RegisterName(Register reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
   return cpu_reg_names[reg];
 }
 
 
 static const char* fpu_reg_names[kNumberOfFpuRegisters] = {
-  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
-  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
+  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
 #ifdef VFPv3_D32
-  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
-  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
+  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
 #endif
 };
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM