| OLD | NEW | 
|---|
| 1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// | 1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// | 
| 2 // | 2 // | 
| 3 //                        The Subzero Code Generator | 3 //                        The Subzero Code Generator | 
| 4 // | 4 // | 
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source | 
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. | 
| 7 // | 7 // | 
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// | 
| 9 /// | 9 /// | 
| 10 /// \file | 10 /// \file | 
| (...skipping 868 matching lines...) Expand 10 before | Expand all | Expand 10 after  Loading... | 
| 879   Ostream &Str = Ctx->getStrEmit(); | 879   Ostream &Str = Ctx->getStrEmit(); | 
| 880   if (Var->hasReg()) { | 880   if (Var->hasReg()) { | 
| 881     const bool Is64BitSandboxing = Traits::Is64Bit && NeedSandboxing; | 881     const bool Is64BitSandboxing = Traits::Is64Bit && NeedSandboxing; | 
| 882     const Type VarType = (Var->isRematerializable() && Is64BitSandboxing) | 882     const Type VarType = (Var->isRematerializable() && Is64BitSandboxing) | 
| 883                              ? IceType_i64 | 883                              ? IceType_i64 | 
| 884                              : Var->getType(); | 884                              : Var->getType(); | 
| 885     Str << "%" << getRegName(Var->getRegNum(), VarType); | 885     Str << "%" << getRegName(Var->getRegNum(), VarType); | 
| 886     return; | 886     return; | 
| 887   } | 887   } | 
| 888   if (Var->mustHaveReg()) { | 888   if (Var->mustHaveReg()) { | 
| 889     llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName(Func) + | 889     llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName() + | 
| 890                              ") has no register assigned - function " + | 890                              ") has no register assigned - function " + | 
| 891                              Func->getFunctionName()); | 891                              Func->getFunctionName()); | 
| 892   } | 892   } | 
| 893   const int32_t Offset = Var->getStackOffset(); | 893   const int32_t Offset = Var->getStackOffset(); | 
| 894   auto BaseRegNum = Var->getBaseRegNum(); | 894   auto BaseRegNum = Var->getBaseRegNum(); | 
| 895   if (BaseRegNum.hasNoValue()) | 895   if (BaseRegNum.hasNoValue()) | 
| 896     BaseRegNum = getFrameOrStackReg(); | 896     BaseRegNum = getFrameOrStackReg(); | 
| 897   // Print in the form "Offset(%reg)", taking care that: | 897   // Print in the form "Offset(%reg)", taking care that: | 
| 898   //   - Offset is never printed when it is 0 | 898   //   - Offset is never printed when it is 0 | 
| 899 | 899 | 
| 900   const bool DecorateAsm = getFlags().getDecorateAsm(); | 900   const bool DecorateAsm = getFlags().getDecorateAsm(); | 
| 901   // Only print Offset when it is nonzero, regardless of DecorateAsm. | 901   // Only print Offset when it is nonzero, regardless of DecorateAsm. | 
| 902   if (Offset) { | 902   if (Offset) { | 
| 903     if (DecorateAsm) { | 903     if (DecorateAsm) { | 
| 904       Str << Var->getSymbolicStackOffset(Func); | 904       Str << Var->getSymbolicStackOffset(); | 
| 905     } else { | 905     } else { | 
| 906       Str << Offset; | 906       Str << Offset; | 
| 907     } | 907     } | 
| 908   } | 908   } | 
| 909   const Type FrameSPTy = Traits::WordType; | 909   const Type FrameSPTy = Traits::WordType; | 
| 910   Str << "(%" << getRegName(BaseRegNum, FrameSPTy) << ")"; | 910   Str << "(%" << getRegName(BaseRegNum, FrameSPTy) << ")"; | 
| 911 } | 911 } | 
| 912 | 912 | 
| 913 template <typename TraitsType> | 913 template <typename TraitsType> | 
| 914 typename TargetX86Base<TraitsType>::X86Address | 914 typename TargetX86Base<TraitsType>::X86Address | 
| 915 TargetX86Base<TraitsType>::stackVarToAsmOperand(const Variable *Var) const { | 915 TargetX86Base<TraitsType>::stackVarToAsmOperand(const Variable *Var) const { | 
| 916   if (Var->hasReg()) | 916   if (Var->hasReg()) | 
| 917     llvm::report_fatal_error("Stack Variable has a register assigned"); | 917     llvm::report_fatal_error("Stack Variable has a register assigned"); | 
| 918   if (Var->mustHaveReg()) { | 918   if (Var->mustHaveReg()) { | 
| 919     llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName(Func) + | 919     llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName() + | 
| 920                              ") has no register assigned - function " + | 920                              ") has no register assigned - function " + | 
| 921                              Func->getFunctionName()); | 921                              Func->getFunctionName()); | 
| 922   } | 922   } | 
| 923   int32_t Offset = Var->getStackOffset(); | 923   int32_t Offset = Var->getStackOffset(); | 
| 924   auto BaseRegNum = Var->getBaseRegNum(); | 924   auto BaseRegNum = Var->getBaseRegNum(); | 
| 925   if (Var->getBaseRegNum().hasNoValue()) | 925   if (Var->getBaseRegNum().hasNoValue()) | 
| 926     BaseRegNum = getFrameOrStackReg(); | 926     BaseRegNum = getFrameOrStackReg(); | 
| 927   return X86Address(Traits::getEncodedGPR(BaseRegNum), Offset, | 927   return X86Address(Traits::getEncodedGPR(BaseRegNum), Offset, | 
| 928                     AssemblerFixup::NoFixup); | 928                     AssemblerFixup::NoFixup); | 
| 929 } | 929 } | 
| (...skipping 572 matching lines...) Expand 10 before | Expand all | Expand 10 after  Loading... | 
| 1502       } | 1502       } | 
| 1503       ++NumGprArgs; | 1503       ++NumGprArgs; | 
| 1504       RegisterArg = Func->makeVariable(Ty); | 1504       RegisterArg = Func->makeVariable(Ty); | 
| 1505     } | 1505     } | 
| 1506     assert(RegNum.hasValue()); | 1506     assert(RegNum.hasValue()); | 
| 1507     assert(RegisterArg != nullptr); | 1507     assert(RegisterArg != nullptr); | 
| 1508     // Replace Arg in the argument list with the home register. Then generate | 1508     // Replace Arg in the argument list with the home register. Then generate | 
| 1509     // an instruction in the prolog to copy the home register to the assigned | 1509     // an instruction in the prolog to copy the home register to the assigned | 
| 1510     // location of Arg. | 1510     // location of Arg. | 
| 1511     if (BuildDefs::dump()) | 1511     if (BuildDefs::dump()) | 
| 1512       RegisterArg->setName(Func, "home_reg:" + Arg->getName(Func)); | 1512       RegisterArg->setName(Func, "home_reg:" + Arg->getName()); | 
| 1513     RegisterArg->setRegNum(RegNum); | 1513     RegisterArg->setRegNum(RegNum); | 
| 1514     RegisterArg->setIsArg(); | 1514     RegisterArg->setIsArg(); | 
| 1515     Arg->setIsArg(false); | 1515     Arg->setIsArg(false); | 
| 1516 | 1516 | 
| 1517     Args[i] = RegisterArg; | 1517     Args[i] = RegisterArg; | 
| 1518     Context.insert<InstAssign>(Arg, RegisterArg); | 1518     Context.insert<InstAssign>(Arg, RegisterArg); | 
| 1519   } | 1519   } | 
| 1520 } | 1520 } | 
| 1521 | 1521 | 
| 1522 /// Strength-reduce scalar integer multiplication by a constant (for i32 or | 1522 /// Strength-reduce scalar integer multiplication by a constant (for i32 or | 
| (...skipping 5898 matching lines...) Expand 10 before | Expand all | Expand 10 after  Loading... | 
| 7421         emitGlobal(*Var, SectionSuffix); | 7421         emitGlobal(*Var, SectionSuffix); | 
| 7422       } | 7422       } | 
| 7423     } | 7423     } | 
| 7424   } break; | 7424   } break; | 
| 7425   } | 7425   } | 
| 7426 } | 7426 } | 
| 7427 } // end of namespace X86NAMESPACE | 7427 } // end of namespace X86NAMESPACE | 
| 7428 } // end of namespace Ice | 7428 } // end of namespace Ice | 
| 7429 | 7429 | 
| 7430 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H | 7430 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H | 
| OLD | NEW | 
|---|