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Issue 1862993002: [arm] Implement Float(32|64)(Min|Max) using vsel. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 8 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <stdarg.h> 5 #include <stdarg.h>
6 #include <stdlib.h> 6 #include <stdlib.h>
7 #include <cmath> 7 #include <cmath>
8 8
9 #if V8_TARGET_ARCH_ARM 9 #if V8_TARGET_ARCH_ARM
10 10
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4021 UNREACHABLE(); // Case analysis is exhaustive. 4021 UNREACHABLE(); // Case analysis is exhaustive.
4022 break; 4022 break;
4023 } 4023 }
4024 sd_value = canonicalizeNaN(sd_value); 4024 sd_value = canonicalizeNaN(sd_value);
4025 set_s_register_from_float(d, sd_value); 4025 set_s_register_from_float(d, sd_value);
4026 } 4026 }
4027 } else { 4027 } else {
4028 UNIMPLEMENTED(); 4028 UNIMPLEMENTED();
4029 } 4029 }
4030 break; 4030 break;
4031 case 0x1C:
4032 if ((instr->Bits(11, 9) == 0x5) && (instr->Bit(6) == 0) &&
4033 (instr->Bit(4) == 0)) {
4034 // VSEL* (floating-point)
4035 bool condition_holds;
4036 switch (instr->Bits(21, 20)) {
4037 case 0x0: // VSELEQ
4038 condition_holds = (z_flag_ == 1);
4039 break;
4040 case 0x1: // VSELVS
4041 condition_holds = (v_flag_ == 1);
4042 break;
4043 case 0x2: // VSELGE
4044 condition_holds = (n_flag_ == v_flag_);
4045 break;
4046 case 0x3: // VSELGT
4047 condition_holds = ((z_flag_ == 0) && (n_flag_ == v_flag_));
4048 break;
4049 default:
4050 UNREACHABLE(); // Case analysis is exhaustive.
4051 break;
4052 }
4053 if (instr->SzValue() == 0x1) {
4054 int n = instr->VFPNRegValue(kDoublePrecision);
4055 int m = instr->VFPMRegValue(kDoublePrecision);
4056 int d = instr->VFPDRegValue(kDoublePrecision);
4057 double result = get_double_from_d_register(condition_holds ? n : m);
4058 set_d_register_from_double(d, result);
4059 } else {
4060 int n = instr->VFPNRegValue(kSinglePrecision);
4061 int m = instr->VFPMRegValue(kSinglePrecision);
4062 int d = instr->VFPDRegValue(kSinglePrecision);
4063 float result = get_float_from_s_register(condition_holds ? n : m);
4064 set_s_register_from_float(d, result);
4065 }
4066 } else {
4067 UNIMPLEMENTED();
4068 }
4069 break;
4031 default: 4070 default:
4032 UNIMPLEMENTED(); 4071 UNIMPLEMENTED();
4033 break; 4072 break;
4034 } 4073 }
4035 } 4074 }
4036 4075
4037 4076
4038 // Executes the current instruction. 4077 // Executes the current instruction.
4039 void Simulator::InstructionDecode(Instruction* instr) { 4078 void Simulator::InstructionDecode(Instruction* instr) {
4040 if (v8::internal::FLAG_check_icache) { 4079 if (v8::internal::FLAG_check_icache) {
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4275 set_register(sp, current_sp + sizeof(uintptr_t)); 4314 set_register(sp, current_sp + sizeof(uintptr_t));
4276 return address; 4315 return address;
4277 } 4316 }
4278 4317
4279 } // namespace internal 4318 } // namespace internal
4280 } // namespace v8 4319 } // namespace v8
4281 4320
4282 #endif // USE_SIMULATOR 4321 #endif // USE_SIMULATOR
4283 4322
4284 #endif // V8_TARGET_ARCH_ARM 4323 #endif // V8_TARGET_ARCH_ARM
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