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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
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1862 } | 1862 } |
1863 break; | 1863 break; |
1864 default: | 1864 default: |
1865 UNREACHABLE(); // Case analysis is exhaustive. | 1865 UNREACHABLE(); // Case analysis is exhaustive. |
1866 break; | 1866 break; |
1867 } | 1867 } |
1868 } else { | 1868 } else { |
1869 Unknown(instr); | 1869 Unknown(instr); |
1870 } | 1870 } |
1871 break; | 1871 break; |
| 1872 case 0x1C: |
| 1873 if ((instr->Bits(11, 9) == 0x5) && (instr->Bit(6) == 0) && |
| 1874 (instr->Bit(4) == 0)) { |
| 1875 // VSEL* (floating-point) |
| 1876 bool dp_operation = (instr->SzValue() == 1); |
| 1877 switch (instr->Bits(21, 20)) { |
| 1878 case 0x0: |
| 1879 if (dp_operation) { |
| 1880 Format(instr, "vseleq.f64 'Dd, 'Dn, 'Dm"); |
| 1881 } else { |
| 1882 Format(instr, "vseleq.f32 'Sd, 'Sn, 'Sm"); |
| 1883 } |
| 1884 break; |
| 1885 case 0x1: |
| 1886 if (dp_operation) { |
| 1887 Format(instr, "vselvs.f64 'Dd, 'Dn, 'Dm"); |
| 1888 } else { |
| 1889 Format(instr, "vselvs.f32 'Sd, 'Sn, 'Sm"); |
| 1890 } |
| 1891 break; |
| 1892 case 0x2: |
| 1893 if (dp_operation) { |
| 1894 Format(instr, "vselge.f64 'Dd, 'Dn, 'Dm"); |
| 1895 } else { |
| 1896 Format(instr, "vselge.f32 'Sd, 'Sn, 'Sm"); |
| 1897 } |
| 1898 break; |
| 1899 case 0x3: |
| 1900 if (dp_operation) { |
| 1901 Format(instr, "vselgt.f64 'Dd, 'Dn, 'Dm"); |
| 1902 } else { |
| 1903 Format(instr, "vselgt.f32 'Sd, 'Sn, 'Sm"); |
| 1904 } |
| 1905 break; |
| 1906 default: |
| 1907 UNREACHABLE(); // Case analysis is exhaustive. |
| 1908 break; |
| 1909 } |
| 1910 } else { |
| 1911 Unknown(instr); |
| 1912 } |
| 1913 break; |
1872 default: | 1914 default: |
1873 Unknown(instr); | 1915 Unknown(instr); |
1874 break; | 1916 break; |
1875 } | 1917 } |
1876 } | 1918 } |
1877 | 1919 |
1878 #undef VERIFIY | 1920 #undef VERIFIY |
1879 | 1921 |
1880 bool Decoder::IsConstantPoolAt(byte* instr_ptr) { | 1922 bool Decoder::IsConstantPoolAt(byte* instr_ptr) { |
1881 int instruction_bits = *(reinterpret_cast<int*>(instr_ptr)); | 1923 int instruction_bits = *(reinterpret_cast<int*>(instr_ptr)); |
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2034 v8::internal::PrintF( | 2076 v8::internal::PrintF( |
2035 f, "%p %08x %s\n", | 2077 f, "%p %08x %s\n", |
2036 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 2078 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
2037 } | 2079 } |
2038 } | 2080 } |
2039 | 2081 |
2040 | 2082 |
2041 } // namespace disasm | 2083 } // namespace disasm |
2042 | 2084 |
2043 #endif // V8_TARGET_ARCH_ARM | 2085 #endif // V8_TARGET_ARCH_ARM |
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