Initial SIMDBC interpreter.

runtime/vm/flow_graph_compiler.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_XXX.
 
 #include "vm/flow_graph_compiler.h"
 
 #include "vm/bit_vector.h"
 #include "vm/cha.h"
@@ skipping 485 matching lines @@
   for (intptr_t i = 0; i < block_order().length(); ++i) {
     // Compile the block entry.
     BlockEntryInstr* entry = block_order()[i];
     assembler()->Comment("B%" Pd "", entry->block_id());
     set_current_block(entry);
 
     if (WasCompacted(entry)) {
       continue;
     }
 
-#if defined(DEBUG)
+#if defined(DEBUG) && !defined(TARGET_ARCH_DBC)
     if (!is_optimizing()) {
       FrameStateClear();
     }
 #endif
 
     LoopInfoComment(assembler(), *entry, *loop_headers);
 
     entry->set_offset(assembler()->CodeSize());
     BeginCodeSourceRange();
     entry->EmitNativeCode(this);
@@ skipping 33 matching lines @@
         BeginCodeSourceRange();
         EmitInstructionPrologue(instr);
         ASSERT(pending_deoptimization_env_ == NULL);
         pending_deoptimization_env_ = instr->env();
         instr->EmitNativeCode(this);
         pending_deoptimization_env_ = NULL;
         EmitInstructionEpilogue(instr);
         EndCodeSourceRange(instr->token_pos());
       }
 
-#if defined(DEBUG)
+#if defined(DEBUG) && !defined(TARGET_ARCH_DBC)
       if (!is_optimizing()) {
         FrameStateUpdateWith(instr);
       }
 #endif
     }
 
-#if defined(DEBUG)
+#if defined(DEBUG) && !defined(TARGET_ARCH_DBC)
     ASSERT(is_optimizing() || FrameStateIsSafeToCall());
 #endif
   }
 
   if (is_optimizing()) {
     LogBlock lb;
     intervals.Add(
         IntervalStruct(prev_offset, prev_inlining_pos, prev_inlining_id));
     inlined_code_intervals_ =
         Array::New(intervals.length() * Code::kInlIntNumEntries, Heap::kOld);
@@ skipping 562 matching lines @@
   // branches from intrinsic code redirect to here where the slow-path
   // (normal function body) starts.
   // This means that there must not be any side-effects in intrinsic code
   // before any deoptimization point.
   ASSERT(!intrinsic_slow_path_label_.IsBound());
   assembler()->Bind(&intrinsic_slow_path_label_);
   return false;
 }
 
 
+// DBC is very different from other architectures in how it performs instance
+// and static calls because it does not use stubs.
+#if !defined(TARGET_ARCH_DBC)
 void FlowGraphCompiler::GenerateInstanceCall(
     intptr_t deopt_id,
     TokenPosition token_pos,
     intptr_t argument_count,
     LocationSummary* locs,
     const ICData& ic_data_in) {
   ICData& ic_data = ICData::ZoneHandle(ic_data_in.Original());
   if (FLAG_precompiled_mode) {
     ic_data = ic_data.AsUnaryClassChecks();
     EmitSwitchableInstanceCall(ic_data, argument_count,
@@ skipping 119 matching lines @@
                                               Label* is_instance_lbl) {
   assembler()->Comment("ListTypeCheck");
   Label unknown;
   GrowableArray<intptr_t> args;
   args.Add(kArrayCid);
   args.Add(kGrowableObjectArrayCid);
   args.Add(kImmutableArrayCid);
   CheckClassIds(kClassIdReg, args, is_instance_lbl, &unknown);
   assembler()->Bind(&unknown);
 }
-
+#endif  // !defined(TARGET_ARCH_DBC)
 
 void FlowGraphCompiler::EmitComment(Instruction* instr) {
   if (!FLAG_support_il_printer || !FLAG_support_disassembler) {
     return;
   }
 #ifndef PRODUCT
   char buffer[256];
   BufferFormatter f(buffer, sizeof(buffer));
   instr->PrintTo(&f);
   assembler()->Comment("%s", buffer);
 #endif
 }
 
 
+#if !defined(TARGET_ARCH_DBC)
+// TODO(vegorov) enable edge-counters on DBC if we consider them beneficial.
 bool FlowGraphCompiler::NeedsEdgeCounter(TargetEntryInstr* block) {
   // Only emit an edge counter if there is not goto at the end of the block,
   // except for the entry block.
   return (FLAG_reorder_basic_blocks
       && (!block->last_instruction()->IsGoto()
           || (block == flow_graph().graph_entry()->normal_entry())));
 }
 
 
 // Allocate a register that is not explicitly blocked.
 static Register AllocateFreeRegister(bool* blocked_registers) {
   for (intptr_t regno = 0; regno < kNumberOfCpuRegisters; regno++) {
     if (!blocked_registers[regno]) {
       blocked_registers[regno] = true;
       return static_cast<Register>(regno);
     }
   }
   UNREACHABLE();
   return kNoRegister;
 }
-
-
-static uword RegMaskBit(Register reg) {
-  return ((reg) != kNoRegister) ? (1 << (reg)) : 0;
-}
+#endif
 
 
 void FlowGraphCompiler::AllocateRegistersLocally(Instruction* instr) {
   ASSERT(!is_optimizing());
-
   instr->InitializeLocationSummary(zone(),
                                    false);  // Not optimizing.
+
+  // No need to allocate registers based on LocationSummary on DBC as in
+  // unoptimized mode it's a stack based bytecode just like IR itself.
+#if !defined(TARGET_ARCH_DBC)
   LocationSummary* locs = instr->locs();
 
   bool blocked_registers[kNumberOfCpuRegisters];
 
   // Block all registers globally reserved by the assembler, etc and mark
   // the rest as free.
   for (intptr_t i = 0; i < kNumberOfCpuRegisters; i++) {
     blocked_registers[i] = (kDartAvailableCpuRegs & (1 << i)) == 0;
   }
 
@@ skipping 69 matching lines @@
         break;
       case Location::kSameAsFirstInput:
         result_location = locs->in(0);
         break;
       case Location::kRequiresFpuRegister:
         UNREACHABLE();
         break;
     }
     locs->set_out(0, result_location);
   }
+#endif  // !defined(TARGET_ARCH_DBC)
 }
 
 
+static uword RegMaskBit(Register reg) {
+  return ((reg) != kNoRegister) ? (1 << (reg)) : 0;
+}
+
+
 ParallelMoveResolver::ParallelMoveResolver(FlowGraphCompiler* compiler)
     : compiler_(compiler), moves_(32) {}
 
 
 void ParallelMoveResolver::EmitNativeCode(ParallelMoveInstr* parallel_move) {
   ASSERT(moves_.is_empty());
   // Build up a worklist of moves.
   BuildInitialMoveList(parallel_move);
 
   for (int i = 0; i < moves_.length(); ++i) {
@@ skipping 393 matching lines @@
     // |token_pos|.
     code_source_map_builder()->AddEntry(saved_code_size_, token_pos);
     BeginCodeSourceRange();
     return true;
   }
 );
   return false;
 }
 
 
+#if !defined(TARGET_ARCH_DBC)
+// DBC emits calls very differently from other architectures due to its
+// interpreted nature.
 void FlowGraphCompiler::EmitPolymorphicInstanceCall(
     const ICData& ic_data,
     intptr_t argument_count,
     const Array& argument_names,
     intptr_t deopt_id,
     TokenPosition token_pos,
     LocationSummary* locs,
     bool complete) {
   if (FLAG_polymorphic_with_deopt) {
     Label* deopt = AddDeoptStub(deopt_id,
@@ skipping 23 matching lines @@
       EmitTestAndCall(ic_data, argument_count, argument_names,
                       slow_path->entry_label(),  // No cid match.
                       &ok,                       // Found cid.
                       deopt_id, token_pos, locs, false);
 
       assembler()->Bind(slow_path->exit_label());
       assembler()->Bind(&ok);
     }
   }
 }
+#endif
 
-
-#if defined(DEBUG)
+#if defined(DEBUG) && !defined(TARGET_ARCH_DBC)
+// TODO(vegorov) re-enable frame state tracking on DBC. It is
+// currently disabled because it relies on LocationSummaries and
+// we don't use them during unoptimized compilation on DBC.
 void FlowGraphCompiler::FrameStateUpdateWith(Instruction* instr) {
   ASSERT(!is_optimizing());
 
   switch (instr->tag()) {
     case Instruction::kPushArgument:
     case Instruction::kPushTemp:
       // Do nothing.
       break;
 
     case Instruction::kDropTemps:
@@ skipping 50 matching lines @@
     }
   }
   return true;
 }
 
 
 void FlowGraphCompiler::FrameStateClear() {
   ASSERT(!is_optimizing());
   frame_state_.TruncateTo(0);
 }
-#endif
+#endif  // defined(DEBUG) && !defined(TARGET_ARCH_DBC)
 
 
 }  // namespace dart