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Issue 1853973002: S390: Use FIEBRA/FIDBRA for FP Floor/Ceil (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // A Disassembler object is used to disassemble a block of code instruction by 5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be 6 // instruction. The default implementation of the NameConverter object can be
7 // overriden to modify register names or to do symbol lookup on addresses. 7 // overriden to modify register names or to do symbol lookup on addresses.
8 // 8 //
9 // The example below will disassemble a block of code and print it to stdout. 9 // The example below will disassemble a block of code and print it to stdout.
10 // 10 //
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301 } 301 }
302 } 302 }
303 303
304 UNREACHABLE(); 304 UNREACHABLE();
305 return -1; 305 return -1;
306 } 306 }
307 307
308 int Decoder::FormatMask(Instruction* instr, const char* format) { 308 int Decoder::FormatMask(Instruction* instr, const char* format) {
309 DCHECK(format[0] == 'm'); 309 DCHECK(format[0] == 'm');
310 int32_t value = 0; 310 int32_t value = 0;
311 if ((format[1] == '1')) { // prints the mask format in bit 8-12 311 if ((format[1] == '1')) { // prints the mask format in bits 8-12
312 value = reinterpret_cast<RRInstruction*>(instr)->R1Value(); 312 value = reinterpret_cast<RRInstruction*>(instr)->R1Value();
313 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", value); 313 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", value);
314 return 2; 314 return 2;
315 } else if (format[1] == '2') { // mask format in bit 16 - 19 315 } else if (format[1] == '2') { // mask format in bits 16-19
316 value = reinterpret_cast<RXInstruction*>(instr)->B2Value(); 316 value = reinterpret_cast<RXInstruction*>(instr)->B2Value();
317 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", value); 317 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", value);
318 return 2; 318 return 2;
319 } else if (format[1] == '3') { // mask format in bits 20-23
320 value = reinterpret_cast<RRFInstruction*>(instr)->M4Value();
321 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", value);
322 return 2;
319 } 323 }
320 324
321 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); 325 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value);
322 return 2; 326 return 2;
323 } 327 }
324 328
325 int Decoder::FormatDisplacement(Instruction* instr, const char* format) { 329 int Decoder::FormatDisplacement(Instruction* instr, const char* format) {
326 DCHECK(format[0] == 'd'); 330 DCHECK(format[0] == 'd');
327 331
328 if (format[1] == '1') { // displacement in 20-31 332 if (format[1] == '1') { // displacement in 20-31
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984 break; 988 break;
985 case MADBR: 989 case MADBR:
986 Format(instr, "madbr\t'f3,'f5,'f6"); 990 Format(instr, "madbr\t'f3,'f5,'f6");
987 break; 991 break;
988 case MSDBR: 992 case MSDBR:
989 Format(instr, "msdbr\t'f3,'f5,'f6"); 993 Format(instr, "msdbr\t'f3,'f5,'f6");
990 break; 994 break;
991 case FLOGR: 995 case FLOGR:
992 Format(instr, "flogr\t'r5,'r6"); 996 Format(instr, "flogr\t'r5,'r6");
993 break; 997 break;
998 case FIEBRA:
999 Format(instr, "fiebra\t'f5,'m2,'f6,'m3");
1000 break;
1001 case FIDBRA:
1002 Format(instr, "fidbra\t'f5,'m2,'f6,'m3");
1003 break;
994 // TRAP4 is used in calling to native function. it will not be generated 1004 // TRAP4 is used in calling to native function. it will not be generated
995 // in native code. 1005 // in native code.
996 case TRAP4: { 1006 case TRAP4: {
997 Format(instr, "trap4"); 1007 Format(instr, "trap4");
998 break; 1008 break;
999 } 1009 }
1000 default: 1010 default:
1001 return false; 1011 return false;
1002 } 1012 }
1003 return true; 1013 return true;
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1402 byte* prev_pc = pc; 1412 byte* prev_pc = pc;
1403 pc += d.InstructionDecode(buffer, pc); 1413 pc += d.InstructionDecode(buffer, pc);
1404 v8::internal::PrintF(f, "%p %08x %s\n", prev_pc, 1414 v8::internal::PrintF(f, "%p %08x %s\n", prev_pc,
1405 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 1415 *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1406 } 1416 }
1407 } 1417 }
1408 1418
1409 } // namespace disasm 1419 } // namespace disasm
1410 1420
1411 #endif // V8_TARGET_ARCH_S390 1421 #endif // V8_TARGET_ARCH_S390
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