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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1048 if (imm8 == 1) { | 1048 if (imm8 == 1) { |
1049 EMIT(0xD1); | 1049 EMIT(0xD1); |
1050 EMIT(0xD8 | dst.code()); | 1050 EMIT(0xD8 | dst.code()); |
1051 } else { | 1051 } else { |
1052 EMIT(0xC1); | 1052 EMIT(0xC1); |
1053 EMIT(0xD8 | dst.code()); | 1053 EMIT(0xD8 | dst.code()); |
1054 EMIT(imm8); | 1054 EMIT(imm8); |
1055 } | 1055 } |
1056 } | 1056 } |
1057 | 1057 |
| 1058 |
1058 void Assembler::ror(Register dst, uint8_t imm8) { | 1059 void Assembler::ror(Register dst, uint8_t imm8) { |
1059 EnsureSpace ensure_space(this); | 1060 EnsureSpace ensure_space(this); |
1060 ASSERT(is_uint5(imm8)); // illegal shift count | 1061 ASSERT(is_uint5(imm8)); // illegal shift count |
1061 if (imm8 == 1) { | 1062 if (imm8 == 1) { |
1062 EMIT(0xD1); | 1063 EMIT(0xD1); |
1063 EMIT(0xC8 | dst.code()); | 1064 EMIT(0xC8 | dst.code()); |
1064 } else { | 1065 } else { |
1065 EMIT(0xC1); | 1066 EMIT(0xC1); |
1066 EMIT(0xC8 | dst.code()); | 1067 EMIT(0xC8 | dst.code()); |
1067 EMIT(imm8); | 1068 EMIT(imm8); |
1068 } | 1069 } |
1069 } | 1070 } |
1070 | 1071 |
| 1072 |
1071 void Assembler::ror_cl(Register dst) { | 1073 void Assembler::ror_cl(Register dst) { |
1072 EnsureSpace ensure_space(this); | 1074 EnsureSpace ensure_space(this); |
1073 EMIT(0xD3); | 1075 EMIT(0xD3); |
1074 EMIT(0xC8 | dst.code()); | 1076 EMIT(0xC8 | dst.code()); |
1075 } | 1077 } |
1076 | 1078 |
1077 | 1079 |
1078 void Assembler::sar(Register dst, uint8_t imm8) { | 1080 void Assembler::sar(Register dst, uint8_t imm8) { |
1079 EnsureSpace ensure_space(this); | 1081 EnsureSpace ensure_space(this); |
1080 ASSERT(is_uint5(imm8)); // illegal shift count | 1082 ASSERT(is_uint5(imm8)); // illegal shift count |
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2130 EnsureSpace ensure_space(this); | 2132 EnsureSpace ensure_space(this); |
2131 EMIT(0x66); | 2133 EMIT(0x66); |
2132 EMIT(0x0F); | 2134 EMIT(0x0F); |
2133 EMIT(0x3A); | 2135 EMIT(0x3A); |
2134 EMIT(0x0B); | 2136 EMIT(0x0B); |
2135 emit_sse_operand(dst, src); | 2137 emit_sse_operand(dst, src); |
2136 // Mask precision exeption. | 2138 // Mask precision exeption. |
2137 EMIT(static_cast<byte>(mode) | 0x8); | 2139 EMIT(static_cast<byte>(mode) | 0x8); |
2138 } | 2140 } |
2139 | 2141 |
| 2142 |
2140 void Assembler::movmskpd(Register dst, XMMRegister src) { | 2143 void Assembler::movmskpd(Register dst, XMMRegister src) { |
2141 ASSERT(IsEnabled(SSE2)); | 2144 ASSERT(IsEnabled(SSE2)); |
2142 EnsureSpace ensure_space(this); | 2145 EnsureSpace ensure_space(this); |
2143 EMIT(0x66); | 2146 EMIT(0x66); |
2144 EMIT(0x0F); | 2147 EMIT(0x0F); |
2145 EMIT(0x50); | 2148 EMIT(0x50); |
2146 emit_sse_operand(dst, src); | 2149 emit_sse_operand(dst, src); |
2147 } | 2150 } |
2148 | 2151 |
2149 | 2152 |
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2695 fprintf(coverage_log, "%s\n", file_line); | 2698 fprintf(coverage_log, "%s\n", file_line); |
2696 fflush(coverage_log); | 2699 fflush(coverage_log); |
2697 } | 2700 } |
2698 } | 2701 } |
2699 | 2702 |
2700 #endif | 2703 #endif |
2701 | 2704 |
2702 } } // namespace v8::internal | 2705 } } // namespace v8::internal |
2703 | 2706 |
2704 #endif // V8_TARGET_ARCH_IA32 | 2707 #endif // V8_TARGET_ARCH_IA32 |
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