Keep two empty lines between declarations for cpp files

src/x64/disasm-x64.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 31 matching lines @@
   UNSET_OP_ORDER = 0,
   // Operand size decides between 16, 32 and 64 bit operands.
   REG_OPER_OP_ORDER = 1,  // Register destination, operand source.
   OPER_REG_OP_ORDER = 2,  // Operand destination, register source.
   // Fixed 8-bit operands.
   BYTE_SIZE_OPERAND_FLAG = 4,
   BYTE_REG_OPER_OP_ORDER = REG_OPER_OP_ORDER | BYTE_SIZE_OPERAND_FLAG,
   BYTE_OPER_REG_OP_ORDER = OPER_REG_OP_ORDER | BYTE_SIZE_OPERAND_FLAG
 };
 
+
 //------------------------------------------------------------------
 // Tables
 //------------------------------------------------------------------
 struct ByteMnemonic {
   int b;  // -1 terminates, otherwise must be in range (0..255)
   OperandType op_order_;
   const char* mnem;
 };
 
 
@@ skipping 224 matching lines @@
   {"cmovs", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovns", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovpe", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovpo", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovl", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovge", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovle", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false},
   {"cmovg", TWO_OPERANDS_INSTR, REG_OPER_OP_ORDER, false}
 };
 
+
 //------------------------------------------------------------------------------
 // DisassemblerX64 implementation.
 
 enum UnimplementedOpcodeAction {
   CONTINUE_ON_UNIMPLEMENTED_OPCODE,
   ABORT_ON_UNIMPLEMENTED_OPCODE
 };
 
+
 // A new DisassemblerX64 object is created to disassemble each instruction.
 // The object can only disassemble a single instruction.
 class DisassemblerX64 {
  public:
   DisassemblerX64(const NameConverter& converter,
                   UnimplementedOpcodeAction unimplemented_action =
                       ABORT_ON_UNIMPLEMENTED_OPCODE)
       : converter_(converter),
         tmp_buffer_pos_(0),
         abort_on_unimplemented_(
@@ skipping 1442 matching lines @@
   }
   for (int i = 6 - instr_len; i >= 0; i--) {
     outp += v8::internal::OS::SNPrintF(out_buffer + outp, "  ");
   }
 
   outp += v8::internal::OS::SNPrintF(out_buffer + outp, " %s",
                                      tmp_buffer_.start());
   return instr_len;
 }
 
+
 //------------------------------------------------------------------------------
 
 
 static const char* cpu_regs[16] = {
   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
 };
 
 
 static const char* byte_cpu_regs[16] = {
@@ skipping 39 matching lines @@
   return "noxmmreg";
 }
 
 
 const char* NameConverter::NameInCode(byte* addr) const {
   // X64 does not embed debug strings at the moment.
   UNREACHABLE();
   return "";
 }
 
+
 //------------------------------------------------------------------------------
 
 Disassembler::Disassembler(const NameConverter& converter)
     : converter_(converter) { }
 
 Disassembler::~Disassembler() { }
 
 
 int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
                                     byte* instruction) {
@@ skipping 25 matching lines @@
     for (int i = 6 - static_cast<int>(pc - prev_pc); i >= 0; i--) {
       fprintf(f, "  ");
     }
     fprintf(f, "  %s\n", buffer.start());
   }
 }
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_X64