Simplify references to command line flags.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 334 matching lines @@
 }
 
 template <typename TraitsType>
 TargetX86Base<TraitsType>::TargetX86Base(Cfg *Func)
     : TargetLowering(Func), NeedSandboxing(SandboxingType == ST_NaCl) {
   static_assert(
       (Traits::InstructionSet::End - Traits::InstructionSet::Begin) ==
           (TargetInstructionSet::X86InstructionSet_End -
            TargetInstructionSet::X86InstructionSet_Begin),
       "Traits::InstructionSet range different from TargetInstructionSet");
-  if (Func->getContext()->getFlags().getTargetInstructionSet() !=
+  if (getFlags().getTargetInstructionSet() !=
       TargetInstructionSet::BaseInstructionSet) {
     InstructionSet = static_cast<InstructionSetEnum>(
-        (Func->getContext()->getFlags().getTargetInstructionSet() -
+        (getFlags().getTargetInstructionSet() -
          TargetInstructionSet::X86InstructionSet_Begin) +
         Traits::InstructionSet::Begin);
   }
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::staticInit(GlobalContext *Ctx) {
   RegNumT::setLimit(Traits::RegisterSet::Reg_NUM);
-  Traits::initRegisterSet(Ctx->getFlags(), &TypeToRegisterSet,
-                          &RegisterAliases);
+  Traits::initRegisterSet(getFlags(), &TypeToRegisterSet, &RegisterAliases);
   for (size_t i = 0; i < TypeToRegisterSet.size(); ++i)
     TypeToRegisterSetUnfiltered[i] = TypeToRegisterSet[i];
   filterTypeToRegisterSet(Ctx, Traits::RegisterSet::Reg_NUM,
                           TypeToRegisterSet.data(), TypeToRegisterSet.size(),
                           Traits::getRegName, getRegClassName);
   PcRelFixup = Traits::FK_PcRel;
-  AbsFixup =
-      Ctx->getFlags().getUseNonsfi() ? Traits::FK_Gotoff : Traits::FK_Abs;
+  AbsFixup = getFlags().getUseNonsfi() ? Traits::FK_Gotoff : Traits::FK_Abs;
 }
 
 template <typename TraitsType>
 bool TargetX86Base<TraitsType>::shouldBePooled(const Constant *C) {
   if (auto *ConstFloat = llvm::dyn_cast<ConstantFloat>(C)) {
     return !Utils::isPositiveZero(ConstFloat->getValue());
   }
   if (auto *ConstDouble = llvm::dyn_cast<ConstantDouble>(C)) {
     return !Utils::isPositiveZero(ConstDouble->getValue());
   }
-  if (GlobalContext::getFlags().getRandomizeAndPoolImmediatesOption() !=
-      RPI_Pool) {
+  if (getFlags().getRandomizeAndPoolImmediatesOption() != RPI_Pool) {
     return false;
   }
   return C->shouldBeRandomizedOrPooled();
 }
 
 template <typename TraitsType> void TargetX86Base<TraitsType>::translateO2() {
   TimerMarker T(TimerStack::TT_O2, Func);
 
   if (SandboxingType != ST_None) {
     initRebasePtr();
   }
 
   genTargetHelperCalls();
   Func->dump("After target helper call insertion");
 
   // Merge Alloca instructions, and lay out the stack.
   static constexpr bool SortAndCombineAllocas = true;
   Func->processAllocas(SortAndCombineAllocas);
   Func->dump("After Alloca processing");
 
-  if (!Ctx->getFlags().getEnablePhiEdgeSplit()) {
+  if (!getFlags().getEnablePhiEdgeSplit()) {
     // Lower Phi instructions.
     Func->placePhiLoads();
     if (Func->hasError())
       return;
     Func->placePhiStores();
     if (Func->hasError())
       return;
     Func->deletePhis();
     if (Func->hasError())
       return;
@@ skipping 65 matching lines @@
   assert(Func->validateLiveness());
   // The post-codegen dump is done here, after liveness analysis and associated
   // cleanup, to make the dump cleaner and more useful.
   Func->dump("After initial x8632 codegen");
   Func->getVMetadata()->init(VMK_All);
   regAlloc(RAK_Global);
   if (Func->hasError())
     return;
   Func->dump("After linear scan regalloc");
 
-  if (Ctx->getFlags().getEnablePhiEdgeSplit()) {
+  if (getFlags().getEnablePhiEdgeSplit()) {
     Func->advancedPhiLowering();
     Func->dump("After advanced Phi lowering");
   }
 
   // Stack frame mapping.
   Func->genFrame();
   if (Func->hasError())
     return;
   Func->dump("After stack frame mapping");
 
@@ skipping 387 matching lines @@
                              ") has no register assigned - function " +
                              Func->getFunctionName());
   }
   const int32_t Offset = Var->getStackOffset();
   auto BaseRegNum = Var->getBaseRegNum();
   if (BaseRegNum.hasNoValue())
     BaseRegNum = getFrameOrStackReg();
   // Print in the form "Offset(%reg)", taking care that:
   //   - Offset is never printed when it is 0
 
-  const bool DecorateAsm = Func->getContext()->getFlags().getDecorateAsm();
+  const bool DecorateAsm = getFlags().getDecorateAsm();
   // Only print Offset when it is nonzero, regardless of DecorateAsm.
   if (Offset) {
     if (DecorateAsm) {
       Str << Var->getSymbolicStackOffset(Func);
     } else {
       Str << Offset;
     }
   }
   const Type FrameSPTy = Traits::WordType;
   Str << "(%" << getRegName(BaseRegNum, FrameSPTy) << ")";
@@ skipping 458 matching lines @@
     return legalize(MemOperand);
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
 template <typename TraitsType>
 SmallBitVector
 TargetX86Base<TraitsType>::getRegisterSet(RegSetMask Include,
                                           RegSetMask Exclude) const {
-  return Traits::getRegisterSet(Ctx->getFlags(), Include, Exclude);
+  return Traits::getRegisterSet(getFlags(), Include, Exclude);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerAlloca(const InstAlloca *Instr) {
   // Conservatively require the stack to be aligned. Some stack adjustment
   // operations implemented below assume that the stack is aligned before the
   // alloca. All the alloca code ensures that the stack alignment is preserved
   // after the alloca. The stack alignment restriction can be relaxed in some
   // cases.
   NeedsStackAlignment = true;
 
   // For default align=0, set it to the real value 1, to avoid any
   // bit-manipulation problems below.
   const uint32_t AlignmentParam = std::max(1u, Instr->getAlignInBytes());
 
   // LLVM enforces power of 2 alignment.
   assert(llvm::isPowerOf2_32(AlignmentParam));
   assert(llvm::isPowerOf2_32(Traits::X86_STACK_ALIGNMENT_BYTES));
 
   const uint32_t Alignment =
       std::max(AlignmentParam, Traits::X86_STACK_ALIGNMENT_BYTES);
   const bool OverAligned = Alignment > Traits::X86_STACK_ALIGNMENT_BYTES;
-  const bool OptM1 = Ctx->getFlags().getOptLevel() == Opt_m1;
+  const bool OptM1 = getFlags().getOptLevel() == Opt_m1;
   const bool AllocaWithKnownOffset = Instr->getKnownFrameOffset();
   const bool UseFramePointer =
       hasFramePointer() || OverAligned || !AllocaWithKnownOffset || OptM1;
 
   if (UseFramePointer)
     setHasFramePointer();
 
   Variable *esp = getPhysicalRegister(getStackReg(), Traits::WordType);
   if (OverAligned) {
     _and(esp, Ctx->getConstantInt32(-Alignment));
@@ skipping 109 matching lines @@
 /// Strength-reduce scalar integer multiplication by a constant (for i32 or
 /// narrower) for certain constants. The lea instruction can be used to multiply
 /// by 3, 5, or 9, and the lsh instruction can be used to multiply by powers of
 /// 2. These can be combined such that e.g. multiplying by 100 can be done as 2
 /// lea-based multiplies by 5, combined with left-shifting by 2.
 template <typename TraitsType>
 bool TargetX86Base<TraitsType>::optimizeScalarMul(Variable *Dest, Operand *Src0,
                                                   int32_t Src1) {
   // Disable this optimization for Om1 and O0, just to keep things simple
   // there.
-  if (Ctx->getFlags().getOptLevel() < Opt_1)
+  if (getFlags().getOptLevel() < Opt_1)
     return false;
   Type Ty = Dest->getType();
   if (Src1 == -1) {
     Variable *T = nullptr;
     _mov(T, Src0);
     _neg(T);
     _mov(Dest, T);
     return true;
   }
   if (Src1 == 0) {
@@ skipping 673 matching lines @@
     }
     T_edx = makeReg(Ty, Edx);
     _mov(T, Src0, Eax);
     _mov(T_edx, Ctx->getConstantZero(Ty));
     _div(T, Src1, T_edx);
     _mov(Dest, T);
   } break;
   case InstArithmetic::Sdiv:
     // TODO(stichnot): Enable this after doing better performance and cross
     // testing.
-    if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
+    if (false && getFlags().getOptLevel() >= Opt_1) {
       // Optimize division by constant power of 2, but not for Om1 or O0, just
       // to keep things simple there.
       if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
         const int32_t Divisor = C->getValue();
         const uint32_t UDivisor = Divisor;
         if (Divisor > 0 && llvm::isPowerOf2_32(UDivisor)) {
           uint32_t LogDiv = llvm::Log2_32(UDivisor);
           // LLVM does the following for dest=src/(1<<log):
           //   t=src
           //   sar t,typewidth-1 // -1 if src is negative, 0 if not
@@ skipping 69 matching lines @@
     }
     T_edx = makeReg(Ty, Edx);
     _mov(T_edx, Ctx->getConstantZero(Ty));
     _mov(T, Src0, Eax);
     _div(T_edx, Src1, T);
     _mov(Dest, T_edx);
   } break;
   case InstArithmetic::Srem: {
     // TODO(stichnot): Enable this after doing better performance and cross
     // testing.
-    if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
+    if (false && getFlags().getOptLevel() >= Opt_1) {
       // Optimize mod by constant power of 2, but not for Om1 or O0, just to
       // keep things simple there.
       if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
         const int32_t Divisor = C->getValue();
         const uint32_t UDivisor = Divisor;
         if (Divisor > 0 && llvm::isPowerOf2_32(UDivisor)) {
           uint32_t LogDiv = llvm::Log2_32(UDivisor);
           // LLVM does the following for dest=src%(1<<log):
           //   t=src
           //   sar t,typewidth-1 // -1 if src is negative, 0 if not
@@ skipping 1972 matching lines @@
   constexpr bool Locked = true;
   _cmpxchg(Addr, T_eax, DesiredReg, Locked);
   _mov(DestPrev, T_eax);
 }
 
 template <typename TraitsType>
 bool TargetX86Base<TraitsType>::tryOptimizedCmpxchgCmpBr(Variable *Dest,
                                                          Operand *PtrToMem,
                                                          Operand *Expected,
                                                          Operand *Desired) {
-  if (Ctx->getFlags().getOptLevel() == Opt_m1)
+  if (getFlags().getOptLevel() == Opt_m1)
     return false;
   // Peek ahead a few instructions and see how Dest is used.
   // It's very common to have:
   //
   // %x = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* ptr, i32 %expected, ...)
   // [%y_phi = ...] // list of phi stores
   // %p = icmp eq i32 %x, %expected
   // br i1 %p, label %l1, label %l2
   //
   // which we can optimize into:
@@ skipping 949 matching lines @@
 
   // If the Base has more than one use or is live across multiple blocks, then
   // don't go further. Alternatively (?), never consider a transformation that
   // would change a variable that is currently *not* live across basic block
   // boundaries into one that *is*.
   if (Func->getVMetadata()->isMultiBlock(
           NewAddr.Base) /* || Base->getUseCount() > 1*/)
     return nullptr;
 
   AddressOptimizer AddrOpt(Func);
-  const bool MockBounds = Func->getContext()->getFlags().getMockBoundsCheck();
+  const bool MockBounds = getFlags().getMockBoundsCheck();
   const Inst *Reason = nullptr;
   bool AddressWasOptimized = false;
   // The following unnamed struct identifies the address mode formation steps
   // that could potentially create an invalid memory operand (i.e., no free
   // slots for RebasePtr.) We add all those variables to this struct so that we
   // can use memset() to reset all members to false.
   struct {
     bool AssignBase = false;
     bool AssignIndex = false;
     bool OffsetFromBase = false;
@@ skipping 171 matching lines @@
 ///   cmp reg, 0
 ///   je label
 ///   cmp reg, 1
 ///   je label
 ///   label:
 ///
 /// Also note that we don't need to add a bounds check to a dereference of a
 /// simple global variable address.
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::doMockBoundsCheck(Operand *Opnd) {
-  if (!Ctx->getFlags().getMockBoundsCheck())
+  if (!getFlags().getMockBoundsCheck())
     return;
   if (auto *Mem = llvm::dyn_cast<X86OperandMem>(Opnd)) {
     if (Mem->getIndex()) {
       llvm::report_fatal_error("doMockBoundsCheck: Opnd contains index reg");
     }
     Opnd = Mem->getBase();
   }
   // At this point Opnd could be nullptr, or Variable, or Constant, or perhaps
   // something else.  We only care if it is Variable.
   auto *Var = llvm::dyn_cast_or_null<Variable>(Opnd);
@@ skipping 699 matching lines @@
   } else {
     TargetLowering::lowerOther(Instr);
   }
 }
 
 /// Turn an i64 Phi instruction into a pair of i32 Phi instructions, to preserve
 /// integrity of liveness analysis. Undef values are also turned into zeroes,
 /// since loOperand() and hiOperand() don't expect Undef input.  Also, in
 /// Non-SFI mode, add a FakeUse(RebasePtr) for every pooled constant operand.
 template <typename TraitsType> void TargetX86Base<TraitsType>::prelowerPhis() {
-  if (Ctx->getFlags().getUseNonsfi()) {
+  if (getFlags().getUseNonsfi()) {
     assert(RebasePtr);
     CfgNode *Node = Context.getNode();
     uint32_t RebasePtrUseCount = 0;
     for (Inst &I : Node->getPhis()) {
       auto *Phi = llvm::dyn_cast<InstPhi>(&I);
       if (Phi->isDeleted())
         continue;
       for (SizeT I = 0; I < Phi->getSrcSize(); ++I) {
         Operand *Src = Phi->getSrc(I);
         // TODO(stichnot): This over-counts for +0.0, and under-counts for other
@@ skipping 506 matching lines @@
     _movp(Reg, Src);
   } else {
     _mov(Reg, Src);
   }
   return Reg;
 }
 
 template <typename TraitsType>
 Operand *TargetX86Base<TraitsType>::legalize(Operand *From, LegalMask Allowed,
                                              RegNumT RegNum) {
-  const bool UseNonsfi = Func->getContext()->getFlags().getUseNonsfi();
+  const bool UseNonsfi = getFlags().getUseNonsfi();
   const Type Ty = From->getType();
   // Assert that a physical register is allowed. To date, all calls to
   // legalize() allow a physical register. If a physical register needs to be
   // explicitly disallowed, then new code will need to be written to force a
   // spill.
   assert(Allowed & Legal_Reg);
   // If we're asking for a specific physical register, make sure we're not
   // allowing any other operand kinds. (This could be future work, e.g. allow
   // the shl shift amount to be either an immediate or in ecx.)
   assert(RegNum.hasNoValue() || Allowed == Legal_Reg);
@@ skipping 276 matching lines @@
   uint32_t TyIndex = llvm::findLastSet(Size, llvm::ZB_Undefined);
   if (!llvm::isPowerOf2_32(Size))
     ++TyIndex;
   uint32_t MaxIndex = MaxSize == NoSizeLimit
                           ? llvm::array_lengthof(TypeForSize) - 1
                           : llvm::findLastSet(MaxSize, llvm::ZB_Undefined);
   return TypeForSize[std::min(TyIndex, MaxIndex)];
 }
 
 template <typename TraitsType> void TargetX86Base<TraitsType>::postLower() {
-  if (Ctx->getFlags().getOptLevel() == Opt_m1)
+  if (getFlags().getOptLevel() == Opt_m1)
     return;
   markRedefinitions();
   Context.availabilityUpdate();
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::makeRandomRegisterPermutation(
     llvm::SmallVectorImpl<RegNumT> &Permutation,
     const SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
-  Traits::makeRandomRegisterPermutation(Ctx, Func, Permutation,
-                                        ExcludeRegisters, Salt);
+  Traits::makeRandomRegisterPermutation(Func, Permutation, ExcludeRegisters,
+                                        Salt);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::emit(const ConstantInteger32 *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   Str << "$" << C->getValue();
 }
 
@@ skipping 27 matching lines @@
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::emit(const ConstantUndef *) const {
   llvm::report_fatal_error("undef value encountered by emitter.");
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::emit(const ConstantRelocatable *C) const {
   if (!BuildDefs::dump())
     return;
-  assert(!Ctx->getFlags().getUseNonsfi() ||
+  assert(!getFlags().getUseNonsfi() ||
          C->getName().toString() == GlobalOffsetTable);
   Ostream &Str = Ctx->getStrEmit();
   Str << "$";
   emitWithoutPrefix(C);
 }
 
 /// Randomize or pool an Immediate.
 template <typename TraitsType>
 Operand *
 TargetX86Base<TraitsType>::randomizeOrPoolImmediate(Constant *Immediate,
                                                     RegNumT RegNum) {
   assert(llvm::isa<ConstantInteger32>(Immediate) ||
          llvm::isa<ConstantRelocatable>(Immediate));
-  if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
+  if (getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
       RandomizationPoolingPaused == true) {
     // Immediates randomization/pooling off or paused
     return Immediate;
   }
 
   if (Traits::Is64Bit && NeedSandboxing) {
     // Immediate randomization/pooling is currently disabled for x86-64
     // sandboxing for it could generate invalid memory operands.
     assert(false &&
            "Constant pooling/randomization is disabled for x8664 sandbox.");
     return Immediate;
   }
 
   if (!Immediate->shouldBeRandomizedOrPooled()) {
     // the constant Immediate is not eligible for blinding/pooling
     return Immediate;
   }
   Ctx->statsUpdateRPImms();
-  switch (Ctx->getFlags().getRandomizeAndPoolImmediatesOption()) {
+  switch (getFlags().getRandomizeAndPoolImmediatesOption()) {
   default:
     llvm::report_fatal_error("Unsupported -randomize-pool-immediates option");
   case RPI_Randomize: {
     // blind the constant
     // FROM:
     //  imm
     // TO:
     //  insert: mov imm+cookie, Reg
     //  insert: lea -cookie[Reg], Reg
     //  => Reg
@@ skipping 16 matching lines @@
     _mov(TruncReg, Reg);
     return TruncReg;
   }
   case RPI_Pool: {
     // pool the constant
     // FROM:
     //  imm
     // TO:
     //  insert: mov $label, Reg
     //  => Reg
-    assert(Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_Pool);
+    assert(getFlags().getRandomizeAndPoolImmediatesOption() == RPI_Pool);
     assert(Immediate->getShouldBePooled());
     // if we have already assigned a phy register, we must come from
     // advancedPhiLowering()=>lowerAssign(). In this case we should reuse the
     // assigned register as this assignment is that start of its use-def
     // chain. So we add RegNum argument here.
     Variable *Reg = makeReg(Immediate->getType(), RegNum);
     constexpr RelocOffsetT Offset = 0;
     Constant *Symbol = Ctx->getConstantSym(Offset, Immediate->getLabelName());
     constexpr Variable *NoBase = nullptr;
     X86OperandMem *MemOperand =
         X86OperandMem::create(Func, Immediate->getType(), NoBase, Symbol);
     _mov(Reg, MemOperand);
     return Reg;
   }
   }
 }
 
 template <typename TraitsType>
 typename TargetX86Base<TraitsType>::X86OperandMem *
 TargetX86Base<TraitsType>::randomizeOrPoolImmediate(X86OperandMem *MemOperand,
                                                     RegNumT RegNum) {
   assert(MemOperand);
-  if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
+  if (getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
       RandomizationPoolingPaused == true) {
     // immediates randomization/pooling is turned off
     return MemOperand;
   }
 
   if (Traits::Is64Bit && NeedSandboxing) {
     // Immediate randomization/pooling is currently disabled for x86-64
     // sandboxing for it could generate invalid memory operands.
     assert(false &&
            "Constant pooling/randomization is disabled for x8664 sandbox.");
@@ skipping 10 matching lines @@
   if (C == nullptr) {
     return MemOperand;
   }
 
   if (!C->shouldBeRandomizedOrPooled()) {
     return MemOperand;
   }
 
   // The offset of this mem operand should be blinded or pooled
   Ctx->statsUpdateRPImms();
-  switch (Ctx->getFlags().getRandomizeAndPoolImmediatesOption()) {
+  switch (getFlags().getRandomizeAndPoolImmediatesOption()) {
   default:
     llvm::report_fatal_error("Unsupported -randomize-pool-immediates option");
   case RPI_Randomize: {
     // blind the constant offset
     // FROM:
     //  offset[base, index, shift]
     // TO:
     //  insert: lea offset+cookie[base], RegTemp
     //  => -cookie[RegTemp, index, shift]
     uint32_t Value =
@@ skipping 65 matching lines @@
   }
   }
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::emitJumpTable(
     const Cfg *Func, const InstJumpTable *JumpTable) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
-  const bool UseNonsfi = Ctx->getFlags().getUseNonsfi();
+  const bool UseNonsfi = getFlags().getUseNonsfi();
   GlobalString FunctionName = Func->getFunctionName();
   const char *Prefix = UseNonsfi ? ".data.rel.ro." : ".rodata.";
   Str << "\t.section\t" << Prefix << FunctionName
       << "$jumptable,\"a\",@progbits\n";
   Str << "\t.align\t" << typeWidthInBytes(getPointerType()) << "\n";
   Str << InstJumpTable::makeName(FunctionName, JumpTable->getId()) << ":";
 
   // On X86 ILP32 pointers are 32-bit hence the use of .long
   for (SizeT I = 0; I < JumpTable->getNumTargets(); ++I)
     Str << "\n\t.long\t" << JumpTable->getTarget(I)->getAsmName();
   Str << "\n";
 }
 
 template <typename TraitsType>
 template <typename T>
 void TargetDataX86<TraitsType>::emitConstantPool(GlobalContext *Ctx) {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   Type Ty = T::Ty;
   SizeT Align = typeAlignInBytes(Ty);
   ConstantList Pool = Ctx->getConstantPool(Ty);
 
   Str << "\t.section\t.rodata.cst" << Align << ",\"aM\",@progbits," << Align
       << "\n";
   Str << "\t.align\t" << Align << "\n";
 
   // If reorder-pooled-constants option is set to true, we need to shuffle the
   // constant pool before emitting it.
-  if (Ctx->getFlags().getReorderPooledConstants() && !Pool.empty()) {
+  if (getFlags().getReorderPooledConstants() && !Pool.empty()) {
     // Use the constant's kind value as the salt for creating random number
     // generator.
     Operand::OperandKind K = (*Pool.begin())->getKind();
-    RandomNumberGenerator RNG(Ctx->getFlags().getRandomSeed(),
+    RandomNumberGenerator RNG(getFlags().getRandomSeed(),
                               RPE_PooledConstantReordering, K);
     RandomShuffle(Pool.begin(), Pool.end(),
                   [&RNG](uint64_t N) { return (uint32_t)RNG.next(N); });
   }
 
   for (Constant *C : Pool) {
     if (!C->getShouldBePooled())
       continue;
     auto *Const = llvm::cast<typename T::IceType>(C);
     typename T::IceType::PrimType Value = Const->getValue();
     // Use memcpy() to copy bits from Value into RawValue in a way that avoids
     // breaking strict-aliasing rules.
     typename T::PrimitiveIntType RawValue;
     memcpy(&RawValue, &Value, sizeof(Value));
     char buf[30];
     int CharsPrinted =
         snprintf(buf, llvm::array_lengthof(buf), T::PrintfString, RawValue);
     assert(CharsPrinted >= 0);
     assert((size_t)CharsPrinted < llvm::array_lengthof(buf));
     (void)CharsPrinted; // avoid warnings if asserts are disabled
     Str << Const->getLabelName();
     Str << ":\n\t" << T::AsmTag << "\t" << buf << "\t/* " << T::TypeName << " "
         << Value << " */\n";
   }
 }
 
 template <typename TraitsType>
 void TargetDataX86<TraitsType>::lowerConstants() {
-  if (Ctx->getFlags().getDisableTranslation())
+  if (getFlags().getDisableTranslation())
     return;
-  switch (Ctx->getFlags().getOutFileType()) {
+  switch (getFlags().getOutFileType()) {
   case FT_Elf: {
     ELFObjectWriter *Writer = Ctx->getObjectWriter();
 
     Writer->writeConstantPool<ConstantInteger32>(IceType_i8);
     Writer->writeConstantPool<ConstantInteger32>(IceType_i16);
     Writer->writeConstantPool<ConstantInteger32>(IceType_i32);
 
     Writer->writeConstantPool<ConstantFloat>(IceType_f32);
     Writer->writeConstantPool<ConstantDouble>(IceType_f64);
   } break;
   case FT_Asm:
   case FT_Iasm: {
     OstreamLocker L(Ctx);
 
     emitConstantPool<PoolTypeConverter<uint8_t>>(Ctx);
     emitConstantPool<PoolTypeConverter<uint16_t>>(Ctx);
     emitConstantPool<PoolTypeConverter<uint32_t>>(Ctx);
 
     emitConstantPool<PoolTypeConverter<float>>(Ctx);
     emitConstantPool<PoolTypeConverter<double>>(Ctx);
   } break;
   }
 }
 
 template <typename TraitsType>
 void TargetDataX86<TraitsType>::lowerJumpTables() {
-  const bool IsPIC = Ctx->getFlags().getUseNonsfi();
-  switch (Ctx->getFlags().getOutFileType()) {
+  const bool IsPIC = getFlags().getUseNonsfi();
+  switch (getFlags().getOutFileType()) {
   case FT_Elf: {
     ELFObjectWriter *Writer = Ctx->getObjectWriter();
     for (const JumpTableData &JT : Ctx->getJumpTables())
       Writer->writeJumpTable(JT, Traits::FK_Abs, IsPIC);
   } break;
   case FT_Asm:
     // Already emitted from Cfg
     break;
   case FT_Iasm: {
     if (!BuildDefs::dump())
@@ skipping 11 matching lines @@
         Str << "\n\t.long\t" << JT.getFunctionName() << "+" << TargetOffset;
       Str << "\n";
     }
   } break;
   }
 }
 
 template <typename TraitsType>
 void TargetDataX86<TraitsType>::lowerGlobals(
     const VariableDeclarationList &Vars, const std::string &SectionSuffix) {
-  const bool IsPIC = Ctx->getFlags().getUseNonsfi();
-  switch (Ctx->getFlags().getOutFileType()) {
+  const bool IsPIC = getFlags().getUseNonsfi();
+  switch (getFlags().getOutFileType()) {
   case FT_Elf: {
     ELFObjectWriter *Writer = Ctx->getObjectWriter();
     Writer->writeDataSection(Vars, Traits::FK_Abs, SectionSuffix, IsPIC);
   } break;
   case FT_Asm:
   case FT_Iasm: {
-    const std::string TranslateOnly = Ctx->getFlags().getTranslateOnly();
+    const std::string TranslateOnly = getFlags().getTranslateOnly();
     OstreamLocker L(Ctx);
     for (const VariableDeclaration *Var : Vars) {
       if (GlobalContext::matchSymbolName(Var->getName(), TranslateOnly)) {
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H