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1 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=// | 1 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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608 Registers[RegisterSet::val] = false; \ | 608 Registers[RegisterSet::val] = false; \ |
609 } | 609 } |
610 | 610 |
611 REGX8664_TABLE | 611 REGX8664_TABLE |
612 | 612 |
613 #undef X | 613 #undef X |
614 | 614 |
615 return Registers; | 615 return Registers; |
616 } | 616 } |
617 | 617 |
618 static void | 618 static void makeRandomRegisterPermutation( |
619 makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func, | 619 Cfg *Func, llvm::SmallVectorImpl<RegNumT> &Permutation, |
620 llvm::SmallVectorImpl<RegNumT> &Permutation, | 620 const SmallBitVector &ExcludeRegisters, uint64_t Salt) { |
621 const SmallBitVector &ExcludeRegisters, | |
622 uint64_t Salt) { | |
623 // TODO(stichnot): Declaring Permutation this way loses type/size | 621 // TODO(stichnot): Declaring Permutation this way loses type/size |
624 // information. Fix this in conjunction with the caller-side TODO. | 622 // information. Fix this in conjunction with the caller-side TODO. |
625 assert(Permutation.size() >= RegisterSet::Reg_NUM); | 623 assert(Permutation.size() >= RegisterSet::Reg_NUM); |
626 // Expected upper bound on the number of registers in a single equivalence | 624 // Expected upper bound on the number of registers in a single equivalence |
627 // class. For x86-64, this would comprise the 16 XMM registers. This is | 625 // class. For x86-64, this would comprise the 16 XMM registers. This is |
628 // for performance, not correctness. | 626 // for performance, not correctness. |
629 static const unsigned MaxEquivalenceClassSize = 8; | 627 static const unsigned MaxEquivalenceClassSize = 8; |
630 using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>; | 628 using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>; |
631 using EquivalenceClassMap = std::map<uint32_t, RegisterList>; | 629 using EquivalenceClassMap = std::map<uint32_t, RegisterList>; |
632 EquivalenceClassMap EquivalenceClasses; | 630 EquivalenceClassMap EquivalenceClasses; |
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657 Index |= (is32To8 << (AttrKey++)); \ | 655 Index |= (is32To8 << (AttrKey++)); \ |
658 Index |= (is64To8 << (AttrKey++)); \ | 656 Index |= (is64To8 << (AttrKey++)); \ |
659 Index |= (isTrunc8Rcvr << (AttrKey++)); \ | 657 Index |= (isTrunc8Rcvr << (AttrKey++)); \ |
660 /* val is assigned to an equivalence class based on its properties. */ \ | 658 /* val is assigned to an equivalence class based on its properties. */ \ |
661 EquivalenceClasses[Index].push_back(RegisterSet::val); \ | 659 EquivalenceClasses[Index].push_back(RegisterSet::val); \ |
662 } | 660 } |
663 REGX8664_TABLE | 661 REGX8664_TABLE |
664 #undef X | 662 #undef X |
665 | 663 |
666 // Create a random number generator for regalloc randomization. | 664 // Create a random number generator for regalloc randomization. |
667 RandomNumberGenerator RNG(Ctx->getFlags().getRandomSeed(), | 665 RandomNumberGenerator RNG(getFlags().getRandomSeed(), |
668 RPE_RegAllocRandomization, Salt); | 666 RPE_RegAllocRandomization, Salt); |
669 RandomNumberGeneratorWrapper RNGW(RNG); | 667 RandomNumberGeneratorWrapper RNGW(RNG); |
670 | 668 |
671 // Shuffle the resulting equivalence classes. | 669 // Shuffle the resulting equivalence classes. |
672 for (auto I : EquivalenceClasses) { | 670 for (auto I : EquivalenceClasses) { |
673 const RegisterList &List = I.second; | 671 const RegisterList &List = I.second; |
674 RegisterList Shuffled(List); | 672 RegisterList Shuffled(List); |
675 RandomShuffle(Shuffled.begin(), Shuffled.end(), RNGW); | 673 RandomShuffle(Shuffled.begin(), Shuffled.end(), RNGW); |
676 for (size_t SI = 0, SE = Shuffled.size(); SI < SE; ++SI) { | 674 for (size_t SI = 0, SE = Shuffled.size(); SI < SE; ++SI) { |
677 Permutation[List[SI]] = Shuffled[SI]; | 675 Permutation[List[SI]] = Shuffled[SI]; |
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1032 const char *FldString; // s, l, or <blank> | 1030 const char *FldString; // s, l, or <blank> |
1033 } TypeAttributes[]; | 1031 } TypeAttributes[]; |
1034 }; | 1032 }; |
1035 | 1033 |
1036 using Traits = ::Ice::X8664::TargetX8664Traits; | 1034 using Traits = ::Ice::X8664::TargetX8664Traits; |
1037 } // end of namespace X8664 | 1035 } // end of namespace X8664 |
1038 | 1036 |
1039 } // end of namespace Ice | 1037 } // end of namespace Ice |
1040 | 1038 |
1041 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H | 1039 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H |
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