OLD | NEW |
1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// | 1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
(...skipping 553 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
564 if (frameptr && (Exclude & ::Ice::TargetLowering::RegSet_FramePointer)) \ | 564 if (frameptr && (Exclude & ::Ice::TargetLowering::RegSet_FramePointer)) \ |
565 Registers[RegisterSet::val] = false; | 565 Registers[RegisterSet::val] = false; |
566 | 566 |
567 REGX8632_TABLE | 567 REGX8632_TABLE |
568 | 568 |
569 #undef X | 569 #undef X |
570 | 570 |
571 return Registers; | 571 return Registers; |
572 } | 572 } |
573 | 573 |
574 static void | 574 static void makeRandomRegisterPermutation( |
575 makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func, | 575 Cfg *Func, llvm::SmallVectorImpl<RegNumT> &Permutation, |
576 llvm::SmallVectorImpl<RegNumT> &Permutation, | 576 const SmallBitVector &ExcludeRegisters, uint64_t Salt) { |
577 const SmallBitVector &ExcludeRegisters, | |
578 uint64_t Salt) { | |
579 // TODO(stichnot): Declaring Permutation this way loses type/size | 577 // TODO(stichnot): Declaring Permutation this way loses type/size |
580 // information. Fix this in conjunction with the caller-side TODO. | 578 // information. Fix this in conjunction with the caller-side TODO. |
581 assert(Permutation.size() >= RegisterSet::Reg_NUM); | 579 assert(Permutation.size() >= RegisterSet::Reg_NUM); |
582 // Expected upper bound on the number of registers in a single equivalence | 580 // Expected upper bound on the number of registers in a single equivalence |
583 // class. For x86-32, this would comprise the 8 XMM registers. This is for | 581 // class. For x86-32, this would comprise the 8 XMM registers. This is for |
584 // performance, not correctness. | 582 // performance, not correctness. |
585 static const unsigned MaxEquivalenceClassSize = 8; | 583 static const unsigned MaxEquivalenceClassSize = 8; |
586 using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>; | 584 using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>; |
587 using EquivalenceClassMap = std::map<uint32_t, RegisterList>; | 585 using EquivalenceClassMap = std::map<uint32_t, RegisterList>; |
588 EquivalenceClassMap EquivalenceClasses; | 586 EquivalenceClassMap EquivalenceClasses; |
(...skipping 24 matching lines...) Expand all Loading... |
613 Index |= (is32To8 << (AttrKey++)); \ | 611 Index |= (is32To8 << (AttrKey++)); \ |
614 Index |= (is64To8 << (AttrKey++)); \ | 612 Index |= (is64To8 << (AttrKey++)); \ |
615 Index |= (isTrunc8Rcvr << (AttrKey++)); \ | 613 Index |= (isTrunc8Rcvr << (AttrKey++)); \ |
616 /* val is assigned to an equivalence class based on its properties. */ \ | 614 /* val is assigned to an equivalence class based on its properties. */ \ |
617 EquivalenceClasses[Index].push_back(RegisterSet::val); \ | 615 EquivalenceClasses[Index].push_back(RegisterSet::val); \ |
618 } | 616 } |
619 REGX8632_TABLE | 617 REGX8632_TABLE |
620 #undef X | 618 #undef X |
621 | 619 |
622 // Create a random number generator for regalloc randomization. | 620 // Create a random number generator for regalloc randomization. |
623 RandomNumberGenerator RNG(Ctx->getFlags().getRandomSeed(), | 621 RandomNumberGenerator RNG(getFlags().getRandomSeed(), |
624 RPE_RegAllocRandomization, Salt); | 622 RPE_RegAllocRandomization, Salt); |
625 RandomNumberGeneratorWrapper RNGW(RNG); | 623 RandomNumberGeneratorWrapper RNGW(RNG); |
626 | 624 |
627 // Shuffle the resulting equivalence classes. | 625 // Shuffle the resulting equivalence classes. |
628 for (auto I : EquivalenceClasses) { | 626 for (auto I : EquivalenceClasses) { |
629 const RegisterList &List = I.second; | 627 const RegisterList &List = I.second; |
630 RegisterList Shuffled(List); | 628 RegisterList Shuffled(List); |
631 RandomShuffle(Shuffled.begin(), Shuffled.end(), RNGW); | 629 RandomShuffle(Shuffled.begin(), Shuffled.end(), RNGW); |
632 for (size_t SI = 0, SE = Shuffled.size(); SI < SE; ++SI) { | 630 for (size_t SI = 0, SE = Shuffled.size(); SI < SE; ++SI) { |
633 Permutation[List[SI]] = Shuffled[SI]; | 631 Permutation[List[SI]] = Shuffled[SI]; |
(...skipping 357 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
991 | 989 |
992 static uint8_t InstSegmentPrefixes[]; | 990 static uint8_t InstSegmentPrefixes[]; |
993 }; | 991 }; |
994 | 992 |
995 using Traits = ::Ice::X8632::TargetX8632Traits; | 993 using Traits = ::Ice::X8632::TargetX8632Traits; |
996 } // end of namespace X8632 | 994 } // end of namespace X8632 |
997 | 995 |
998 } // end of namespace Ice | 996 } // end of namespace Ice |
999 | 997 |
1000 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H | 998 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H |
OLD | NEW |