Simplify references to command line flags.

src/IceTargetLoweringX8632Traits.h

 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 553 matching lines @@
   if (frameptr && (Exclude & ::Ice::TargetLowering::RegSet_FramePointer))      \
     Registers[RegisterSet::val] = false;
 
     REGX8632_TABLE
 
 #undef X
 
     return Registers;
   }
 
-  static void
-  makeRandomRegisterPermutation(GlobalContext *Ctx, Cfg *Func,
-                                llvm::SmallVectorImpl<RegNumT> &Permutation,
-                                const SmallBitVector &ExcludeRegisters,
-                                uint64_t Salt) {
+  static void makeRandomRegisterPermutation(
+      Cfg *Func, llvm::SmallVectorImpl<RegNumT> &Permutation,
+      const SmallBitVector &ExcludeRegisters, uint64_t Salt) {
     // TODO(stichnot): Declaring Permutation this way loses type/size
     // information. Fix this in conjunction with the caller-side TODO.
     assert(Permutation.size() >= RegisterSet::Reg_NUM);
     // Expected upper bound on the number of registers in a single equivalence
     // class. For x86-32, this would comprise the 8 XMM registers. This is for
     // performance, not correctness.
     static const unsigned MaxEquivalenceClassSize = 8;
     using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>;
     using EquivalenceClassMap = std::map<uint32_t, RegisterList>;
     EquivalenceClassMap EquivalenceClasses;
@@ skipping 24 matching lines @@
     Index |= (is32To8 << (AttrKey++));                                         \
     Index |= (is64To8 << (AttrKey++));                                         \
     Index |= (isTrunc8Rcvr << (AttrKey++));                                    \
     /* val is assigned to an equivalence class based on its properties. */     \
     EquivalenceClasses[Index].push_back(RegisterSet::val);                     \
   }
     REGX8632_TABLE
 #undef X
 
     // Create a random number generator for regalloc randomization.
-    RandomNumberGenerator RNG(Ctx->getFlags().getRandomSeed(),
+    RandomNumberGenerator RNG(getFlags().getRandomSeed(),
                               RPE_RegAllocRandomization, Salt);
     RandomNumberGeneratorWrapper RNGW(RNG);
 
     // Shuffle the resulting equivalence classes.
     for (auto I : EquivalenceClasses) {
       const RegisterList &List = I.second;
       RegisterList Shuffled(List);
       RandomShuffle(Shuffled.begin(), Shuffled.end(), RNGW);
       for (size_t SI = 0, SE = Shuffled.size(); SI < SE; ++SI) {
         Permutation[List[SI]] = Shuffled[SI];
@@ skipping 357 matching lines @@
 
   static uint8_t InstSegmentPrefixes[];
 };
 
 using Traits = ::Ice::X8632::TargetX8632Traits;
 } // end of namespace X8632
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H