Simplify references to command line flags.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 34 matching lines @@
   return ::Ice::ARM32::TargetDataARM32::create(Ctx);
 }
 
 std::unique_ptr<::Ice::TargetHeaderLowering>
 createTargetHeaderLowering(::Ice::GlobalContext *Ctx) {
   return ::Ice::ARM32::TargetHeaderARM32::create(Ctx);
 }
 
 void staticInit(::Ice::GlobalContext *Ctx) {
   ::Ice::ARM32::TargetARM32::staticInit(Ctx);
-  if (Ctx->getFlags().getUseNonsfi()) {
+  if (Ice::getFlags().getUseNonsfi()) {
     // In nonsfi, we need to reference the _GLOBAL_OFFSET_TABLE_ for accessing
     // globals. The GOT is an external symbol (i.e., it is not defined in the
     // pexe) so we need to register it as such so that ELF emission won't barf
     // on an "unknown" symbol. The GOT is added to the External symbols list
     // here because staticInit() is invoked in a single-thread context.
     Ctx->getConstantExternSym(Ctx->getGlobalString(::Ice::GlobalOffsetTable));
   }
 }
 
 bool shouldBePooled(const ::Ice::Constant *C) {
@@ skipping 227 matching lines @@
   // Add handling of new register classes below.
   case RegARM32::RCARM32_QtoS:
     return "QtoS";
   }
 }
 
 } // end of anonymous namespace
 
 TargetARM32::TargetARM32(Cfg *Func)
     : TargetLowering(Func), NeedSandboxing(SandboxingType == ST_NaCl),
-      CPUFeatures(Func->getContext()->getFlags()) {}
+      CPUFeatures(getFlags()) {}
 
 void TargetARM32::staticInit(GlobalContext *Ctx) {
   RegNumT::setLimit(RegARM32::Reg_NUM);
   // Limit this size (or do all bitsets need to be the same width)???
   SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
   SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
   SmallBitVector Float32Registers(RegARM32::Reg_NUM);
   SmallBitVector Float64Registers(RegARM32::Reg_NUM);
   SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
   SmallBitVector QtoSRegisters(RegARM32::Reg_NUM);
@@ skipping 720 matching lines @@
     createGotPtr();
   }
   genTargetHelperCalls();
   findMaxStackOutArgsSize();
 
   // Do not merge Alloca instructions, and lay out the stack.
   static constexpr bool SortAndCombineAllocas = true;
   Func->processAllocas(SortAndCombineAllocas);
   Func->dump("After Alloca processing");
 
-  if (!Ctx->getFlags().getEnablePhiEdgeSplit()) {
+  if (!getFlags().getEnablePhiEdgeSplit()) {
     // Lower Phi instructions.
     Func->placePhiLoads();
     if (Func->hasError())
       return;
     Func->placePhiStores();
     if (Func->hasError())
       return;
     Func->deletePhis();
     if (Func->hasError())
       return;
@@ skipping 47 matching lines @@
   // cleanup, to make the dump cleaner and more useful.
   Func->dump("After initial ARM32 codegen");
   Func->getVMetadata()->init(VMK_All);
   regAlloc(RAK_Global);
   if (Func->hasError())
     return;
 
   copyRegAllocFromInfWeightVariable64On32(Func->getVariables());
   Func->dump("After linear scan regalloc");
 
-  if (Ctx->getFlags().getEnablePhiEdgeSplit()) {
+  if (getFlags().getEnablePhiEdgeSplit()) {
     Func->advancedPhiLowering();
     Func->dump("After advanced Phi lowering");
   }
 
   ForbidTemporaryWithoutReg _(this);
 
   // Stack frame mapping.
   Func->genFrame();
   if (Func->hasError())
     return;
   Func->dump("After stack frame mapping");
 
   postLowerLegalization();
   if (Func->hasError())
     return;
   Func->dump("After postLowerLegalization");
 
   Func->contractEmptyNodes();
   Func->reorderNodes();
 
   // Branch optimization. This needs to be done just before code emission. In
   // particular, no transformations that insert or reorder CfgNodes should be
   // done after branch optimization. We go ahead and do it before nop insertion
   // to reduce the amount of work needed for searching for opportunities.
   Func->doBranchOpt();
   Func->dump("After branch optimization");
 
   // Nop insertion
-  if (Ctx->getFlags().getShouldDoNopInsertion()) {
+  if (getFlags().getShouldDoNopInsertion()) {
     Func->doNopInsertion();
   }
 }
 
 void TargetARM32::translateOm1() {
   TimerMarker T(TimerStack::TT_Om1, Func);
 
   // TODO(stichnot): share passes with other targets?
   if (SandboxingType == ST_Nonsfi) {
     createGotPtr();
@@ skipping 41 matching lines @@
   if (Func->hasError())
     return;
   Func->dump("After stack frame mapping");
 
   postLowerLegalization();
   if (Func->hasError())
     return;
   Func->dump("After postLowerLegalization");
 
   // Nop insertion
-  if (Ctx->getFlags().getShouldDoNopInsertion()) {
+  if (getFlags().getShouldDoNopInsertion()) {
     Func->doNopInsertion();
   }
 }
 
 uint32_t TargetARM32::getStackAlignment() const {
   return ARM32_STACK_ALIGNMENT_BYTES;
 }
 
 bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   if (auto *Br = llvm::dyn_cast<InstARM32Br>(I)) {
@@ skipping 35 matching lines @@
     // liveness validation errors for saving callee-save registers.
     Func->addImplicitArg(Reg);
     // Don't bother tracking the live range of a named physical register.
     Reg->setIgnoreLiveness();
   }
   return Reg;
 }
 
 void TargetARM32::emitJumpTable(const Cfg *Func,
                                 const InstJumpTable *JumpTable) const {
+  (void)Func;
   (void)JumpTable;
-  UnimplementedError(Func->getContext()->getFlags());
+  UnimplementedError(getFlags());
 }
 
 void TargetARM32::emitVariable(const Variable *Var) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   if (Var->hasReg()) {
     Str << getRegName(Var->getRegNum(), Var->getType());
     return;
   }
@@ skipping 489 matching lines @@
                    Legal_Reg | Legal_Flex, getReservedTmpReg());
       Sandboxer(this).add_sp(AddAmount);
     }
   }
 
   if (!PreservedGPRs.empty())
     _pop(PreservedGPRs);
   if (!PreservedSRegs.empty())
     _pop(PreservedSRegs);
 
-  if (!Ctx->getFlags().getUseSandboxing())
+  if (!getFlags().getUseSandboxing())
     return;
 
   // Change the original ret instruction into a sandboxed return sequence.
   //
   // bundle_lock
   // bic lr, #0xc000000f
   // bx lr
   // bundle_unlock
   //
   // This isn't just aligning to the getBundleAlignLog2Bytes(). It needs to
@@ skipping 467 matching lines @@
   // bit-manipulation problems below.
   const uint32_t AlignmentParam = std::max(1u, Instr->getAlignInBytes());
 
   // LLVM enforces power of 2 alignment.
   assert(llvm::isPowerOf2_32(AlignmentParam));
   assert(llvm::isPowerOf2_32(ARM32_STACK_ALIGNMENT_BYTES));
 
   const uint32_t Alignment =
       std::max(AlignmentParam, ARM32_STACK_ALIGNMENT_BYTES);
   const bool OverAligned = Alignment > ARM32_STACK_ALIGNMENT_BYTES;
-  const bool OptM1 = Ctx->getFlags().getOptLevel() == Opt_m1;
+  const bool OptM1 = getFlags().getOptLevel() == Opt_m1;
   const bool AllocaWithKnownOffset = Instr->getKnownFrameOffset();
   const bool UseFramePointer =
       hasFramePointer() || OverAligned || !AllocaWithKnownOffset || OptM1;
 
   if (UseFramePointer)
     setHasFramePointer();
 
   Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
   if (OverAligned) {
     Sandboxer(this).align_sp(Alignment);
@@ skipping 1080 matching lines @@
     Variable *Src1R = Srcs.unswappedSrc1R(this);
     if (isVectorType(DestTy)) {
       _vsub(T, Src0R, Src1R);
     } else {
       _sub(T, Src0R, Src1R);
     }
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Mul: {
-    const bool OptM1 = Ctx->getFlags().getOptLevel() == Opt_m1;
+    const bool OptM1 = getFlags().getOptLevel() == Opt_m1;
     if (!OptM1 && Srcs.hasConstOperand()) {
       constexpr std::size_t MaxShifts = 4;
       std::array<StrengthReduction::AggregationElement, MaxShifts> Shifts;
       SizeT NumOperations;
       int32_t Const = Srcs.getConstantValue();
       const bool Invert = Const < 0;
       const bool MultiplyByZero = Const == 0;
       Operand *_0 =
           legalize(Ctx->getConstantZero(DestTy), Legal_Reg | Legal_Flex);
 
@@ skipping 2758 matching lines @@
                     TmpRegNum);
     _bic(Reg, Reg, Mask);
   } else {
     Mask = legalize(Ctx->getConstantInt32(-Align), Legal_Reg | Legal_Flex,
                     TmpRegNum);
     _and(Reg, Reg, Mask);
   }
 }
 
 void TargetARM32::postLower() {
-  if (Ctx->getFlags().getOptLevel() == Opt_m1)
+  if (getFlags().getOptLevel() == Opt_m1)
     return;
   markRedefinitions();
   Context.availabilityUpdate();
 }
 
 void TargetARM32::makeRandomRegisterPermutation(
     llvm::SmallVectorImpl<RegNumT> &Permutation,
     const SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
   (void)Permutation;
   (void)ExcludeRegisters;
   (void)Salt;
-  UnimplementedError(Func->getContext()->getFlags());
+  UnimplementedError(getFlags());
 }
 
 void TargetARM32::emit(const ConstantInteger32 *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   Str << "#" << C->getValue();
 }
 
 void TargetARM32::emit(const ConstantInteger64 *) const {
   llvm::report_fatal_error("Not expecting to emit 64-bit integers");
 }
 
 void TargetARM32::emit(const ConstantFloat *C) const {
   (void)C;
-  UnimplementedError(Ctx->getFlags());
+  UnimplementedError(getFlags());
 }
 
 void TargetARM32::emit(const ConstantDouble *C) const {
   (void)C;
-  UnimplementedError(Ctx->getFlags());
+  UnimplementedError(getFlags());
 }
 
 void TargetARM32::emit(const ConstantUndef *) const {
   llvm::report_fatal_error("undef value encountered by emitter.");
 }
 
 void TargetARM32::emit(const ConstantRelocatable *C) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
@@ skipping 532 matching lines @@
   createAutoBundle();
   Target->_sub(SP, SP, SubAmount);
   Target->_bic(SP, SP, memOpBicMask(Target->Func));
 }
 
 TargetDataARM32::TargetDataARM32(GlobalContext *Ctx)
     : TargetDataLowering(Ctx) {}
 
 void TargetDataARM32::lowerGlobals(const VariableDeclarationList &Vars,
                                    const std::string &SectionSuffix) {
-  const bool IsPIC = Ctx->getFlags().getUseNonsfi();
-  switch (Ctx->getFlags().getOutFileType()) {
+  const bool IsPIC = getFlags().getUseNonsfi();
+  switch (getFlags().getOutFileType()) {
   case FT_Elf: {
     ELFObjectWriter *Writer = Ctx->getObjectWriter();
     Writer->writeDataSection(Vars, llvm::ELF::R_ARM_ABS32, SectionSuffix,
                              IsPIC);
   } break;
   case FT_Asm:
   case FT_Iasm: {
-    const std::string TranslateOnly = Ctx->getFlags().getTranslateOnly();
+    const std::string TranslateOnly = getFlags().getTranslateOnly();
     OstreamLocker _(Ctx);
     for (const VariableDeclaration *Var : Vars) {
       if (GlobalContext::matchSymbolName(Var->getName(), TranslateOnly)) {
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 
@@ skipping 59 matching lines @@
   static constexpr size_t MinimumAlignment = 4;
   SizeT Align = std::max(MinimumAlignment, typeAlignInBytes(Traits::IceType));
   assert((Align % 4) == 0 && "Constants should be aligned");
   Ostream &Str = Ctx->getStrEmit();
   ConstantList Pool = Ctx->getConstantPool(Traits::IceType);
 
   Str << "\t.section\t.rodata.cst" << Align << ",\"aM\",%progbits," << Align
       << "\n"
       << "\t.align\t" << Align << "\n";
 
-  if (Ctx->getFlags().getReorderPooledConstants()) {
+  if (getFlags().getReorderPooledConstants()) {
     // TODO(jpp): add constant pooling.
-    UnimplementedError(Ctx->getFlags());
+    UnimplementedError(getFlags());
   }
 
   for (Constant *C : Pool) {
     if (!C->getShouldBePooled()) {
       continue;
     }
 
     emitConstant<T>(Str, llvm::dyn_cast<typename Traits::ConstantType>(C));
   }
 }
 } // end of anonymous namespace
 
 void TargetDataARM32::lowerConstants() {
-  if (Ctx->getFlags().getDisableTranslation())
+  if (getFlags().getDisableTranslation())
     return;
-  switch (Ctx->getFlags().getOutFileType()) {
+  switch (getFlags().getOutFileType()) {
   case FT_Elf: {
     ELFObjectWriter *Writer = Ctx->getObjectWriter();
     Writer->writeConstantPool<ConstantFloat>(IceType_f32);
     Writer->writeConstantPool<ConstantDouble>(IceType_f64);
   } break;
   case FT_Asm:
   case FT_Iasm: {
     OstreamLocker _(Ctx);
     emitConstantPool<float>(Ctx);
     emitConstantPool<double>(Ctx);
     break;
   }
   }
 }
 
 void TargetDataARM32::lowerJumpTables() {
-  if (Ctx->getFlags().getDisableTranslation())
+  if (getFlags().getDisableTranslation())
     return;
-  switch (Ctx->getFlags().getOutFileType()) {
+  switch (getFlags().getOutFileType()) {
   case FT_Elf:
     if (!Ctx->getJumpTables().empty()) {
       llvm::report_fatal_error("ARM32 does not support jump tables yet.");
     }
     break;
   case FT_Asm:
     // Already emitted from Cfg
     break;
   case FT_Iasm: {
     // TODO(kschimpf): Fill this in when we get more information.
     break;
   }
   }
 }
 
 TargetHeaderARM32::TargetHeaderARM32(GlobalContext *Ctx)
-    : TargetHeaderLowering(Ctx), CPUFeatures(Ctx->getFlags()) {}
+    : TargetHeaderLowering(Ctx), CPUFeatures(getFlags()) {}
 
 void TargetHeaderARM32::lower() {
   OstreamLocker _(Ctx);
   Ostream &Str = Ctx->getStrEmit();
   Str << ".syntax unified\n";
   // Emit build attributes in format: .eabi_attribute TAG, VALUE. See Sec. 2 of
   // "Addenda to, and Errata in the ABI for the ARM architecture"
   // http://infocenter.arm.com
   //                  /help/topic/com.arm.doc.ihi0045d/IHI0045D_ABI_addenda.pdf
   //
@@ skipping 33 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice