MIPS: [wasm] Implement Int32MulPair operator.

src/mips/macro-assembler-mips.cc

 
 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>  // For LONG_MIN, LONG_MAX.
 
 #if V8_TARGET_ARCH_MIPS
 
 #include "src/base/bits.h"
@@ skipping 786 matching lines @@
         mul(rd_lo, rs, at);
       } else {
         DCHECK(!rd_hi.is(at) && !rd_lo.is(at));
         mul(rd_lo, rs, at);
         muh(rd_hi, rs, at);
       }
     }
   }
 }
 
+void MacroAssembler::Mulu(Register rd_hi, Register rd_lo, Register rs,
+                          const Operand& rt) {
+  if (rt.is_reg()) {
+    if (!IsMipsArchVariant(kMips32r6)) {
+      multu(rs, rt.rm());
+      mflo(rd_lo);
+      mfhi(rd_hi);
+    } else {
+      if (rd_lo.is(rs)) {
+        DCHECK(!rd_hi.is(rs));
+        DCHECK(!rd_hi.is(rt.rm()) && !rd_lo.is(rt.rm()));
+        muhu(rd_hi, rs, rt.rm());
+        mulu(rd_lo, rs, rt.rm());
+      } else {
+        DCHECK(!rd_hi.is(rt.rm()) && !rd_lo.is(rt.rm()));
+        mulu(rd_lo, rs, rt.rm());
+        muhu(rd_hi, rs, rt.rm());
+      }
+    }
+  } else {
+    // li handles the relocation.
+    DCHECK(!rs.is(at));
+    li(at, rt);
+    if (!IsMipsArchVariant(kMips32r6)) {
+      multu(rs, at);
+      mflo(rd_lo);
+      mfhi(rd_hi);
+    } else {
+      if (rd_lo.is(rs)) {
+        DCHECK(!rd_hi.is(rs));
+        DCHECK(!rd_hi.is(at) && !rd_lo.is(at));
+        muhu(rd_hi, rs, at);
+        mulu(rd_lo, rs, at);
+      } else {
+        DCHECK(!rd_hi.is(at) && !rd_lo.is(at));
+        mulu(rd_lo, rs, at);
+        muhu(rd_hi, rs, at);
+      }
+    }
+  }
+}

[balazs.kilvady, 2016/04/01 12:16:21]

The 2 blocks are almost identical. What do you think about a simpler struct
like:
Register reg;
if (rt.is_reg()) {
  reg = rt.rm();
} else {
  reg = at;
  li(reg, rt);
}
// The 2nd block using reg <-> at. 

[Marija Antic, 2016/04/05 07:50:04]

Done.

 
 void MacroAssembler::Mulh(Register rd, Register rs, const Operand& rt) {
   if (rt.is_reg()) {
     if (!IsMipsArchVariant(kMips32r6)) {
       mult(rs, rt.rm());
       mfhi(rd);
     } else {
       muh(rd, rs, rt.rm());
     }
   } else {
@@ skipping 5412 matching lines @@
   if (mag.shift > 0) sra(result, result, mag.shift);
   srl(at, dividend, 31);
   Addu(result, result, Operand(at));
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS