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Side by Side Diff: src/compiler/s390/code-generator-s390.cc

Issue 1844563002: S390: Fix Div64 sequence + DLGR simulation (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 8 months ago
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1 // Copyright 2015 the V8 project authors. All rights reserved. 1 // Copyright 2015 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/compiler/code-generator.h" 5 #include "src/compiler/code-generator.h"
6 6
7 #include "src/ast/scopes.h" 7 #include "src/ast/scopes.h"
8 #include "src/compiler/code-generator-impl.h" 8 #include "src/compiler/code-generator-impl.h"
9 #include "src/compiler/gap-resolver.h" 9 #include "src/compiler/gap-resolver.h"
10 #include "src/compiler/node-matchers.h" 10 #include "src/compiler/node-matchers.h"
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1100 if (i.OutputDoubleRegister().is(i.InputDoubleRegister(1))) { 1100 if (i.OutputDoubleRegister().is(i.InputDoubleRegister(1))) {
1101 ASSEMBLE_FLOAT_UNOP(mdbr); 1101 ASSEMBLE_FLOAT_UNOP(mdbr);
1102 } else { 1102 } else {
1103 if (!i.OutputDoubleRegister().is(i.InputDoubleRegister(0))) 1103 if (!i.OutputDoubleRegister().is(i.InputDoubleRegister(0)))
1104 __ ldr(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); 1104 __ ldr(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
1105 __ mdbr(i.OutputDoubleRegister(), i.InputDoubleRegister(1)); 1105 __ mdbr(i.OutputDoubleRegister(), i.InputDoubleRegister(1));
1106 } 1106 }
1107 break; 1107 break;
1108 #if V8_TARGET_ARCH_S390X 1108 #if V8_TARGET_ARCH_S390X
1109 case kS390_Div64: 1109 case kS390_Div64:
1110 __ LoadRR(r1, i.InputRegister(0));
1111 __ dsgr(r0, i.InputRegister(1)); // R1: Dividend
1112 __ ltgr(i.OutputRegister(), r1); // Copy R1: Quotient to output
1113 break;
1110 #endif 1114 #endif
1111 case kS390_Div32: 1115 case kS390_Div32:
1112 __ LoadRR(r0, i.InputRegister(0)); 1116 __ LoadRR(r0, i.InputRegister(0));
1113 __ srda(r0, Operand(32)); 1117 __ srda(r0, Operand(32));
1114 __ dr(r0, i.InputRegister(1)); 1118 __ dr(r0, i.InputRegister(1));
1115 __ ltr(i.OutputRegister(), r1); 1119 __ ltr(i.OutputRegister(), r1);
1116 break; 1120 break;
1117 #if V8_TARGET_ARCH_S390X 1121 #if V8_TARGET_ARCH_S390X
1118 case kS390_DivU64: 1122 case kS390_DivU64:
1119 __ LoadRR(r1, i.InputRegister(0)); 1123 __ LoadRR(r1, i.InputRegister(0));
1120 __ LoadImmP(r0, Operand::Zero()); 1124 __ LoadImmP(r0, Operand::Zero());
1121 __ dlgr(r0, i.InputRegister(1)); // R0:R1 = R1 / divisor - 1125 __ dlgr(r0, i.InputRegister(1)); // R0:R1: Dividend
1122 __ ltgr(i.OutputRegister(), r1); // Copy remainder to output reg 1126 __ ltgr(i.OutputRegister(), r1); // Copy R1: Quotient to output
1123 break; 1127 break;
1124 #endif 1128 #endif
1125 case kS390_DivU32: 1129 case kS390_DivU32:
1126 __ LoadRR(r0, i.InputRegister(0)); 1130 __ LoadRR(r0, i.InputRegister(0));
1127 __ srdl(r0, Operand(32)); 1131 __ srdl(r0, Operand(32));
1128 __ dlr(r0, i.InputRegister(1)); // R0:R1 = R1 / divisor - 1132 __ dlr(r0, i.InputRegister(1)); // R0:R1: Dividend
1129 __ ltr(i.OutputRegister(), r1); // Copy remainder to output reg 1133 __ ltr(i.OutputRegister(), r1); // Copy R1: Quotient to output
1130 break; 1134 break;
1131 1135
1132 case kS390_DivFloat: 1136 case kS390_DivFloat:
1133 // InputDoubleRegister(1)=InputDoubleRegister(0)/InputDoubleRegister(1) 1137 // InputDoubleRegister(1)=InputDoubleRegister(0)/InputDoubleRegister(1)
1134 if (i.OutputDoubleRegister().is(i.InputDoubleRegister(1))) { 1138 if (i.OutputDoubleRegister().is(i.InputDoubleRegister(1))) {
1135 __ ldr(kScratchDoubleReg, i.InputDoubleRegister(1)); 1139 __ ldr(kScratchDoubleReg, i.InputDoubleRegister(1));
1136 __ ldr(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); 1140 __ ldr(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
1137 __ debr(i.OutputDoubleRegister(), kScratchDoubleReg); 1141 __ debr(i.OutputDoubleRegister(), kScratchDoubleReg);
1138 } else { 1142 } else {
1139 if (!i.OutputDoubleRegister().is(i.InputDoubleRegister(0))) 1143 if (!i.OutputDoubleRegister().is(i.InputDoubleRegister(0)))
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2058 padding_size -= 2; 2062 padding_size -= 2;
2059 } 2063 }
2060 } 2064 }
2061 } 2065 }
2062 2066
2063 #undef __ 2067 #undef __
2064 2068
2065 } // namespace compiler 2069 } // namespace compiler
2066 } // namespace internal 2070 } // namespace internal
2067 } // namespace v8 2071 } // namespace v8
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