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Side by Side Diff: nss/lib/freebl/rijndael.c

Issue 1843333003: Update NSPR to 4.12 and NSS to 3.23 on iOS (Closed) Base URL: https://chromium.googlesource.com/chromium/deps/nss.git@master
Patch Set: Created 4 years, 8 months ago
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1 /* This Source Code Form is subject to the terms of the Mozilla Public 1 /* This Source Code Form is subject to the terms of the Mozilla Public
2 * License, v. 2.0. If a copy of the MPL was not distributed with this 2 * License, v. 2.0. If a copy of the MPL was not distributed with this
3 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */ 3 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
4 4
5 #ifdef FREEBL_NO_DEPEND 5 #ifdef FREEBL_NO_DEPEND
6 #include "stubs.h" 6 #include "stubs.h"
7 #endif 7 #endif
8 8
9 #include "prinit.h" 9 #include "prinit.h"
10 #include "prenv.h"
10 #include "prerr.h" 11 #include "prerr.h"
11 #include "secerr.h" 12 #include "secerr.h"
12 13
13 #include "prtypes.h" 14 #include "prtypes.h"
14 #include "blapi.h" 15 #include "blapi.h"
15 #include "rijndael.h" 16 #include "rijndael.h"
16 17
17 #include "cts.h" 18 #include "cts.h"
18 #include "ctr.h" 19 #include "ctr.h"
19 #include "gcm.h" 20 #include "gcm.h"
20 21
21 #ifdef USE_HW_AES 22 #ifdef USE_HW_AES
22 #include "intel-aes.h" 23 #include "intel-aes.h"
23 #include "mpi.h" 24 #include "mpi.h"
24 25
25 static int has_intel_aes = 0; 26 static int has_intel_aes = 0;
26 static PRBool use_hw_aes = PR_FALSE; 27 static PRBool use_hw_aes = PR_FALSE;
27 28
28 #ifdef INTEL_GCM 29 #ifdef INTEL_GCM
29 #include "intel-gcm.h" 30 #include "intel-gcm.h"
30 static int has_intel_avx = 0; 31 static int has_intel_avx = 0;
31 static int has_intel_clmul = 0; 32 static int has_intel_clmul = 0;
32 static PRBool use_hw_gcm = PR_FALSE; 33 static PRBool use_hw_gcm = PR_FALSE;
34 #if defined(_MSC_VER) && !defined(_M_IX86)
35 #include <intrin.h> /* for _xgetbv() */
36 #endif
33 #endif 37 #endif
34 #endif /* USE_HW_AES */ 38 #endif /* USE_HW_AES */
35 39
36 /* 40 /*
37 * There are currently five ways to build this code, varying in performance 41 * There are currently five ways to build this code, varying in performance
38 * and code size. 42 * and code size.
39 * 43 *
40 * RIJNDAEL_INCLUDE_TABLES Include all tables from rijndael32.tab 44 * RIJNDAEL_INCLUDE_TABLES Include all tables from rijndael32.tab
41 * RIJNDAEL_GENERATE_TABLES Generate tables on first 45 * RIJNDAEL_GENERATE_TABLES Generate tables on first
42 * encryption/decryption, then store them; 46 * encryption/decryption, then store them;
(...skipping 988 matching lines...) Expand 10 before | Expand all | Expand 10 after
1031 PORT_SetError(SEC_ERROR_INVALID_ARGS); 1035 PORT_SetError(SEC_ERROR_INVALID_ARGS);
1032 return SECFailure; 1036 return SECFailure;
1033 } 1037 }
1034 if (!cx) { 1038 if (!cx) {
1035 PORT_SetError(SEC_ERROR_INVALID_ARGS); 1039 PORT_SetError(SEC_ERROR_INVALID_ARGS);
1036 return SECFailure; 1040 return SECFailure;
1037 } 1041 }
1038 #ifdef USE_HW_AES 1042 #ifdef USE_HW_AES
1039 if (has_intel_aes == 0) { 1043 if (has_intel_aes == 0) {
1040 unsigned long eax, ebx, ecx, edx; 1044 unsigned long eax, ebx, ecx, edx;
1041 » char *disable_hw_aes = getenv("NSS_DISABLE_HW_AES"); 1045 » char *disable_hw_aes = PR_GetEnvSecure("NSS_DISABLE_HW_AES");
1042 1046
1043 if (disable_hw_aes == NULL) { 1047 if (disable_hw_aes == NULL) {
1044 freebl_cpuid(1, &eax, &ebx, &ecx, &edx); 1048 freebl_cpuid(1, &eax, &ebx, &ecx, &edx);
1045 has_intel_aes = (ecx & (1 << 25)) != 0 ? 1 : -1; 1049 has_intel_aes = (ecx & (1 << 25)) != 0 ? 1 : -1;
1046 #ifdef INTEL_GCM 1050 #ifdef INTEL_GCM
1047 has_intel_clmul = (ecx & (1 << 1)) != 0 ? 1 : -1; 1051 has_intel_clmul = (ecx & (1 << 1)) != 0 ? 1 : -1;
1048 if ((ecx & (1 << 27)) != 0 && (ecx & (1 << 28)) != 0 && 1052 if ((ecx & (1 << 27)) != 0 && (ecx & (1 << 28)) != 0 &&
1049 check_xcr0_ymm()) { 1053 check_xcr0_ymm()) {
1050 has_intel_avx = 1; 1054 has_intel_avx = 1;
1051 } else { 1055 } else {
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1314 return SECFailure; 1318 return SECFailure;
1315 } 1319 }
1316 if (maxOutputLen < inputLen) { 1320 if (maxOutputLen < inputLen) {
1317 PORT_SetError(SEC_ERROR_OUTPUT_LEN); 1321 PORT_SetError(SEC_ERROR_OUTPUT_LEN);
1318 return SECFailure; 1322 return SECFailure;
1319 } 1323 }
1320 *outputLen = inputLen; 1324 *outputLen = inputLen;
1321 return (*cx->worker)(cx->worker_cx, output, outputLen, maxOutputLen, 1325 return (*cx->worker)(cx->worker_cx, output, outputLen, maxOutputLen,
1322 input, inputLen, blocksize); 1326 input, inputLen, blocksize);
1323 } 1327 }
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