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1 // Copyright 2010 the V8 project authors. All rights reserved. | 1 // Copyright 2010 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // This file is an internal atomic implementation, use atomicops.h instead. | 5 // This file is an internal atomic implementation, use atomicops.h instead. |
6 // | 6 // |
7 // LinuxKernelCmpxchg and Barrier_AtomicIncrement are from Google Gears. | 7 // LinuxKernelCmpxchg and Barrier_AtomicIncrement are from Google Gears. |
8 | 8 |
9 #ifndef V8_BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_ | 9 #ifndef V8_BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_ |
10 #define V8_BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_ | 10 #define V8_BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_ |
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37 // core devices, this is an empty function that exits immediately. | 37 // core devices, this is an empty function that exits immediately. |
38 // On multi-core devices, it implements a full memory barrier. | 38 // On multi-core devices, it implements a full memory barrier. |
39 // | 39 // |
40 // * This source could be compiled to ARMv5 machine code that runs on a | 40 // * This source could be compiled to ARMv5 machine code that runs on a |
41 // multi-core ARMv6 or ARMv7 device. In this case, memory barriers | 41 // multi-core ARMv6 or ARMv7 device. In this case, memory barriers |
42 // are needed for correct execution. Always call the kernel helper, even | 42 // are needed for correct execution. Always call the kernel helper, even |
43 // when targeting ARMv5TE. | 43 // when targeting ARMv5TE. |
44 // | 44 // |
45 | 45 |
46 inline void MemoryBarrier() { | 46 inline void MemoryBarrier() { |
47 #if defined(__linux__) || defined(__ANDROID__) | 47 #if defined(__ANDROID__) |
48 // Note: This is a function call, which is also an implicit compiler barrier. | 48 // Note: This is a function call, which is also an implicit compiler barrier. |
49 typedef void (*KernelMemoryBarrierFunc)(); | 49 typedef void (*KernelMemoryBarrierFunc)(); |
50 ((KernelMemoryBarrierFunc)0xffff0fa0)(); | 50 ((KernelMemoryBarrierFunc)0xffff0fa0)(); |
51 #elif defined(__QNXNTO__) | 51 #elif defined(__QNXNTO__) |
52 __cpu_membarrier(); | 52 __cpu_membarrier(); |
53 #else | 53 #else |
54 #error MemoryBarrier() is not implemented on this platform. | 54 // Fallback to GCC built-in function |
| 55 __sync_synchronize(); |
55 #endif | 56 #endif |
56 } | 57 } |
57 | 58 |
58 // An ARM toolchain would only define one of these depending on which | 59 // An ARM toolchain would only define one of these depending on which |
59 // variant of the target architecture is being used. This tests against | 60 // variant of the target architecture is being used. This tests against |
60 // any known ARMv6 or ARMv7 variant, where it is possible to directly | 61 // any known ARMv6 or ARMv7 variant, where it is possible to directly |
61 // use ldrex/strex instructions to implement fast atomic operations. | 62 // use ldrex/strex instructions to implement fast atomic operations. |
62 #if defined(__ARM_ARCH_8A__) || \ | 63 #if defined(__ARM_ARCH_8A__) || \ |
63 defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || \ | 64 defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || \ |
64 defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || \ | 65 defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || \ |
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294 inline void NoBarrier_Store(volatile Atomic8* ptr, Atomic8 value) { | 295 inline void NoBarrier_Store(volatile Atomic8* ptr, Atomic8 value) { |
295 *ptr = value; | 296 *ptr = value; |
296 } | 297 } |
297 | 298 |
298 inline Atomic8 NoBarrier_Load(volatile const Atomic8* ptr) { return *ptr; } | 299 inline Atomic8 NoBarrier_Load(volatile const Atomic8* ptr) { return *ptr; } |
299 | 300 |
300 } // namespace base | 301 } // namespace base |
301 } // namespace v8 | 302 } // namespace v8 |
302 | 303 |
303 #endif // V8_BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_ | 304 #endif // V8_BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_ |
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