Subzero: Remove IceString.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 40 matching lines @@
 }
 
 void staticInit(::Ice::GlobalContext *Ctx) {
   ::Ice::ARM32::TargetARM32::staticInit(Ctx);
   if (Ctx->getFlags().getUseNonsfi()) {
     // In nonsfi, we need to reference the _GLOBAL_OFFSET_TABLE_ for accessing
     // globals. The GOT is an external symbol (i.e., it is not defined in the
     // pexe) so we need to register it as such so that ELF emission won't barf
     // on an "unknown" symbol. The GOT is added to the External symbols list
     // here because staticInit() is invoked in a single-thread context.
-    Ctx->getConstantExternSym(::Ice::GlobalOffsetTable);
+    Ctx->getConstantExternSym(Ctx->getGlobalString(::Ice::GlobalOffsetTable));
   }
 }
 
+bool shouldBePooled(const ::Ice::Constant *C) {
+  return ::Ice::ARM32::TargetARM32::shouldBePooled(C);
+}
+
 } // end of namespace ARM32
 
 namespace Ice {
 namespace ARM32 {
 
 namespace {
 
 /// SizeOf is used to obtain the size of an initializer list as a constexpr
 /// expression. This is only needed until our C++ library is updated to
 /// C++ 14 -- which defines constexpr members to std::initializer_list.
@@ skipping 197 matching lines @@
 
 constexpr SizeT NumVec128Args =
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   +(((cc_arg > 0)) ? 1 : 0)
     REGARM32_VEC128_TABLE
 #undef X
     ;
 std::array<RegNumT, NumVec128Args> Vec128ArgInitializer;
 
-IceString getRegClassName(RegClass C) {
+const char *getRegClassName(RegClass C) {
   auto ClassNum = static_cast<RegARM32::RegClassARM32>(C);
   assert(ClassNum < RegARM32::RCARM32_NUM);
   switch (ClassNum) {
   default:
     assert(C < RC_Target);
     return regClassString(C);
   // Add handling of new register classes below.
   case RegARM32::RCARM32_QtoS:
     return "QtoS";
   }
@@ skipping 61 matching lines @@
   TypeToRegisterSet[IceType_v16i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i8] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
   TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
   TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
   TypeToRegisterSet[RegARM32::RCARM32_QtoS] = QtoSRegisters;
 
   for (size_t i = 0; i < llvm::array_lengthof(TypeToRegisterSet); ++i)
     TypeToRegisterSetUnfiltered[i] = TypeToRegisterSet[i];
 
-  filterTypeToRegisterSet(
-      Ctx, RegARM32::Reg_NUM, TypeToRegisterSet,
-      llvm::array_lengthof(TypeToRegisterSet), [](RegNumT RegNum) -> IceString {
-        // This function simply removes ", " from the register name.
-        IceString Name = RegARM32::getRegName(RegNum);
-        constexpr const char RegSeparator[] = ", ";
-        constexpr size_t RegSeparatorWidth =
-            llvm::array_lengthof(RegSeparator) - 1;
-        for (size_t Pos = Name.find(RegSeparator); Pos != std::string::npos;
-             Pos = Name.find(RegSeparator)) {
-          Name.replace(Pos, RegSeparatorWidth, "");
-        }
-        return Name;
-      }, getRegClassName);
+  filterTypeToRegisterSet(Ctx, RegARM32::Reg_NUM, TypeToRegisterSet,
+                          llvm::array_lengthof(TypeToRegisterSet),
+                          [](RegNumT RegNum) -> std::string {
+                            // This function simply removes ", " from the
+                            // register name.
+                            std::string Name = RegARM32::getRegName(RegNum);
+                            constexpr const char RegSeparator[] = ", ";
+                            constexpr size_t RegSeparatorWidth =
+                                llvm::array_lengthof(RegSeparator) - 1;
+                            for (size_t Pos = Name.find(RegSeparator);
+                                 Pos != std::string::npos;
+                                 Pos = Name.find(RegSeparator)) {
+                              Name.replace(Pos, RegSeparatorWidth, "");
+                            }
+                            return Name;
+                          },
+                          getRegClassName);
 }
 
 namespace {
 void copyRegAllocFromInfWeightVariable64On32(const VarList &Vars) {
   for (Variable *Var : Vars) {
     auto *Var64 = llvm::dyn_cast<Variable64On32>(Var);
     if (!Var64) {
       // This is not the variable we are looking for.
       continue;
     }
@@ skipping 395 matching lines @@
       Instr->setDeleted();
       return;
     }
     case Intrinsics::NaClReadTP: {
       if (SandboxingType == ST_NaCl) {
         return;
       }
       static constexpr SizeT MaxArgs = 0;
       Operand *TargetHelper =
           SandboxingType == ST_Nonsfi
-              ? Ctx->getConstantExternSym("__aeabi_read_tp")
+              ? Ctx->getConstantExternSym(
+                    Ctx->getGlobalString("__aeabi_read_tp"))
               : Ctx->getRuntimeHelperFunc(RuntimeHelper::H_call_read_tp);
       Context.insert<InstCall>(MaxArgs, Dest, TargetHelper, NoTailCall,
                                IsTargetHelperCall);
       Instr->setDeleted();
       return;
     }
     case Intrinsics::Setjmp: {
       static constexpr SizeT MaxArgs = 1;
       Operand *TargetHelper =
           Ctx->getRuntimeHelperFunc(RuntimeHelper::H_call_setjmp);
@@ skipping 98 matching lines @@
   //   movt     reg, _GLOBAL_OFFSET_TABLE_ - 12 - .
   //   add      reg, pc, reg
   //   mov      GotPtr, reg
   //
   // If GotPtr is not used, then both these pseudo-instructions are dce'd.
   Variable *T = makeReg(IceType_i32);
   Context.insert<InstFakeDef>(T);
   Context.insert<InstFakeDef>(GotPtr, T);
 }
 
-IceString TargetARM32::createGotoffRelocation(const ConstantRelocatable *CR) {
-  const IceString &CRName = CR->getName();
-  const IceString CRGotoffName =
-      "GOTOFF$" + Func->getFunctionName() + "$" + CRName;
+GlobalString
+TargetARM32::createGotoffRelocation(const ConstantRelocatable *CR) {
+  GlobalString CRName = CR->getName();
+  GlobalString CRGotoffName =
+      Ctx->getGlobalString("GOTOFF$" + Func->getFunctionName() + "$" + CRName);
   if (KnownGotoffs.count(CRGotoffName) == 0) {
     constexpr bool SuppressMangling = true;
     auto *Global =
         VariableDeclaration::create(Func->getGlobalPool(), SuppressMangling);
     Global->setIsConstant(true);
     Global->setName(CRName);
     Func->getGlobalPool()->willNotBeEmitted(Global);
 
     auto *Gotoff =
         VariableDeclaration::create(Func->getGlobalPool(), SuppressMangling);
@@ skipping 32 matching lines @@
 
   if (DefGotPtr == nullptr || DefGotPtr->isDeleted()) {
     return;
   }
 
   // The got addr needs to be materialized at the same point where DefGotPtr
   // lives.
   Context.setInsertPoint(DefGotPtr);
   assert(DefGotPtr->getSrcSize() == 1);
   auto *T = llvm::cast<Variable>(DefGotPtr->getSrc(0));
-  loadNamedConstantRelocatablePIC(GlobalOffsetTable, T,
+  loadNamedConstantRelocatablePIC(Ctx->getGlobalString(GlobalOffsetTable), T,
                                   [this, T](Variable *PC) { _add(T, PC, T); });
   _mov(GotPtr, T);
   DefGotPtr->setDeleted();
 }
 
 void TargetARM32::loadNamedConstantRelocatablePIC(
-    const IceString &Name, Variable *Register,
+    GlobalString Name, Variable *Register,
     std::function<void(Variable *PC)> Finish) {
   assert(SandboxingType == ST_Nonsfi);
   // We makeReg() here instead of getPhysicalRegister() because the latter ends
   // up creating multi-blocks temporaries that liveness fails to validate.
   auto *PC = makeReg(IceType_i32, RegARM32::Reg_pc);
 
   auto *AddPcReloc = RelocOffset::create(Ctx);
   AddPcReloc->setSubtract(true);
   auto *AddPcLabel = InstARM32Label::create(Func, this);
   AddPcLabel->setRelocOffset(AddPcReloc);
 
   auto *MovwReloc = RelocOffset::create(Ctx);
   auto *MovwLabel = InstARM32Label::create(Func, this);
   MovwLabel->setRelocOffset(MovwReloc);
 
   auto *MovtReloc = RelocOffset::create(Ctx);
   auto *MovtLabel = InstARM32Label::create(Func, this);
   MovtLabel->setRelocOffset(MovtReloc);
 
   // The EmitString for these constant relocatables have hardcoded offsets
   // attached to them. This could be dangerous if, e.g., we ever implemented
   // instruction scheduling but llvm-mc currently does not support
   //
   //   movw reg, #:lower16:(Symbol - Label - Number)
   //   movt reg, #:upper16:(Symbol - Label - Number)
   //
   // relocations.
   static constexpr RelocOffsetT PcOffset = -8;
-  auto *CRLower = Ctx->getConstantSym(PcOffset, {MovwReloc, AddPcReloc}, Name,
-                                      Name + " -16");
-  auto *CRUpper = Ctx->getConstantSym(PcOffset, {MovtReloc, AddPcReloc}, Name,
-                                      Name + " -12");
+  auto *CRLower = Ctx->getConstantSymWithEmitString(
+      PcOffset, {MovwReloc, AddPcReloc}, Name, Name + " -16");
+  auto *CRUpper = Ctx->getConstantSymWithEmitString(
+      PcOffset, {MovtReloc, AddPcReloc}, Name, Name + " -12");
 
   Context.insert(MovwLabel);
   _movw(Register, CRLower);
   Context.insert(MovtLabel);
   _movt(Register, CRUpper);
   // PC = fake-def to keep liveness consistent.
   Context.insert<InstFakeDef>(PC);
   Context.insert(AddPcLabel);
   Finish(PC);
 }
@@ skipping 182 matching lines @@
   return ARM32_STACK_ALIGNMENT_BYTES;
 }
 
 bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   if (auto *Br = llvm::dyn_cast<InstARM32Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
-IceString TargetARM32::getRegName(RegNumT RegNum, Type Ty) const {
+const char *TargetARM32::getRegName(RegNumT RegNum, Type Ty) const {
   (void)Ty;
   return RegARM32::getRegName(RegNum);
 }
 
 Variable *TargetARM32::getPhysicalRegister(RegNumT RegNum, Type Ty) {
   static const Type DefaultType[] = {
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
   (isFP32)                                                                     \
       ? IceType_f32                                                            \
@@ skipping 1085 matching lines @@
   _mov(Dest, T);
 }
 
 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) {
   if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi))
     return;
   Variable *SrcLoReg = legalizeToReg(SrcLo);
   switch (Ty) {
   default:
     llvm_unreachable(
-        ("Unexpected type in div0Check: " + typeIceString(Ty)).c_str());
+        ("Unexpected type in div0Check: " + typeStdString(Ty)).c_str());
   case IceType_i8:
   case IceType_i16: {
     Operand *ShAmtImm = shAmtImm(32 - getScalarIntBitWidth(Ty));
     Variable *T = makeReg(IceType_i32);
     _lsls(T, SrcLoReg, ShAmtImm);
     Context.insert<InstFakeUse>(T);
   } break;
   case IceType_i32: {
     _tst(SrcLoReg, SrcLoReg);
     break;
@@ skipping 3629 matching lines @@
         }
         return Reg;
       }
     } else if (auto *C = llvm::dyn_cast<ConstantRelocatable>(From)) {
       Variable *Reg = makeReg(Ty, RegNum);
       if (SandboxingType != ST_Nonsfi) {
         _movw(Reg, C);
         _movt(Reg, C);
       } else {
         auto *GotAddr = legalizeToReg(GotPtr);
-        const IceString CGotoffName = createGotoffRelocation(C);
+        GlobalString CGotoffName = createGotoffRelocation(C);
         loadNamedConstantRelocatablePIC(
             CGotoffName, Reg, [this, Reg](Variable *PC) {
               _ldr(Reg, OperandARM32Mem::create(Func, IceType_i32, PC, Reg));
             });
         _add(Reg, GotAddr, Reg);
       }
       return Reg;
     } else {
       assert(isScalarFloatingType(Ty));
       uint32_t ModifiedImm;
       if (OperandARM32FlexFpImm::canHoldImm(From, &ModifiedImm)) {
         Variable *T = makeReg(Ty, RegNum);
         _mov(T,
              OperandARM32FlexFpImm::create(Func, From->getType(), ModifiedImm));
         return T;
       }
 
       if (Ty == IceType_f64 && isFloatingPointZero(From)) {
         // Use T = T ^ T to load a 64-bit fp zero. This does not work for f32
         // because ARM does not have a veor instruction with S registers.
         Variable *T = makeReg(IceType_f64, RegNum);
         Context.insert<InstFakeDef>(T);
         _veor(T, T, T);
         return T;
       }
 
       // Load floats/doubles from literal pool.
-      std::string Buffer;
-      llvm::raw_string_ostream StrBuf(Buffer);
-      llvm::cast<Constant>(From)->emitPoolLabel(StrBuf);
-      llvm::cast<Constant>(From)->setShouldBePooled(true);
-      Constant *Offset = Ctx->getConstantSym(0, StrBuf.str());
+      auto *CFrom = llvm::cast<Constant>(From);
+      assert(CFrom->getShouldBePooled());
+      Constant *Offset = Ctx->getConstantSym(0, CFrom->getLabelName());
       Variable *BaseReg = nullptr;
       if (SandboxingType == ST_Nonsfi) {
         // vldr does not support the [base, index] addressing mode, so we need
         // to legalize Offset to a register. Otherwise, we could simply
         //   vldr dest, [got, reg(Offset)]
         BaseReg = legalizeToReg(Offset);
       } else {
         BaseReg = makeReg(getPointerType());
         _movw(BaseReg, Offset);
         _movt(BaseReg, Offset);
@@ skipping 697 matching lines @@
   }
   createAutoBundle();
   Target->_sub(SP, SP, SubAmount);
   Target->_bic(SP, SP, memOpBicMask(Target->Func));
 }
 
 TargetDataARM32::TargetDataARM32(GlobalContext *Ctx)
     : TargetDataLowering(Ctx) {}
 
 void TargetDataARM32::lowerGlobals(const VariableDeclarationList &Vars,
-                                   const IceString &SectionSuffix) {
+                                   const std::string &SectionSuffix) {
   const bool IsPIC = Ctx->getFlags().getUseNonsfi();
   switch (Ctx->getFlags().getOutFileType()) {
   case FT_Elf: {
     ELFObjectWriter *Writer = Ctx->getObjectWriter();
     Writer->writeDataSection(Vars, llvm::ELF::R_ARM_ABS32, SectionSuffix,
                              IsPIC);
   } break;
   case FT_Asm:
   case FT_Iasm: {
-    const IceString &TranslateOnly = Ctx->getFlags().getTranslateOnly();
+    const std::string TranslateOnly = Ctx->getFlags().getTranslateOnly();
     OstreamLocker _(Ctx);
     for (const VariableDeclaration *Var : Vars) {
       if (GlobalContext::matchSymbolName(Var->getName(), TranslateOnly)) {
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 
@@ skipping 36 matching lines @@
   }
 };
 const char ConstantPoolEmitterTraits<double>::AsmTag[] = ".quad";
 const char ConstantPoolEmitterTraits<double>::TypeName[] = "f64";
 
 template <typename T>
 void emitConstant(
     Ostream &Str,
     const typename ConstantPoolEmitterTraits<T>::ConstantType *Const) {
   using Traits = ConstantPoolEmitterTraits<T>;
-  Const->emitPoolLabel(Str);
+  Str << Const->getLabelName();
   Str << ":\n\t" << Traits::AsmTag << "\t0x";
   T Value = Const->getValue();
   Str.write_hex(Traits::bitcastToUint64(Value));
   Str << "\t/* " << Traits::TypeName << " " << Value << " */\n";
 }
 
 template <typename T> void emitConstantPool(GlobalContext *Ctx) {
   if (!BuildDefs::dump()) {
     return;
   }
@@ skipping 110 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice