Subzero: Remove IceString.

src/IceInstX8664.cpp

 //===- subzero/src/IceInstX8664.cpp - X86-64 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 120 matching lines @@
       // Emit a non-zero offset without a leading '$'.
       Str << CI->getValue() + Disp;
   } else if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(Offset)) {
     // TODO(sehr): ConstantRelocatable still needs updating for
     // rematerializable base/index and Disp.
     assert(Disp == 0);
     const bool UseNonsfi = Func->getContext()->getFlags().getUseNonsfi();
     CR->emitWithoutPrefix(Target, UseNonsfi ? "@GOTOFF" : "");
     assert(!UseNonsfi);
     if (Base == nullptr && Index == nullptr) {
-      if (CR->getName() != "") { // rip-relative addressing.
-        if (NeedSandboxing) {
-          Str << "(%rip)";
-        } else {
-          Str << "(%eip)";
-        }
+      // rip-relative addressing.
+      if (NeedSandboxing) {
+        Str << "(%rip)";
+      } else {
+        Str << "(%eip)";
       }
     }
   } else {
     llvm_unreachable("Invalid offset type for x86 mem operand");
   }
 
   if (Base == nullptr && Index == nullptr) {
     return;
   }
 
   Str << "(";
   if (Base != nullptr) {
     const Variable *B = Base;
     if (!NeedSandboxing) {
       // TODO(jpp): stop abusing the operand's type to identify LEAs.
       const Type MemType = getType();
       if (Base->getType() != IceType_i32 && MemType != IceType_void) {
         // X86-64 is ILP32, but %rsp and %rbp are accessed as 64-bit registers.
         // For filetype=asm, they need to be emitted as their 32-bit sibilings.
         assert(Base->getType() == IceType_i64);
         assert(Base->getRegNum() == RegX8664::Encoded_Reg_rsp ||
                Base->getRegNum() == RegX8664::Encoded_Reg_rbp ||
                getType() == IceType_void);
-        B = B->asType(IceType_i32, X8664::Traits::getGprForType(
-                                       IceType_i32, Base->getRegNum()));
+        B = B->asType(Func, IceType_i32, X8664::Traits::getGprForType(
+                                             IceType_i32, Base->getRegNum()));
       }
     }
 
     B->emit(Func);
   }
 
   if (Index != nullptr) {
     Variable *I = Index;
     Str << ",";
     I->emit(Func);
@@ skipping 78 matching lines @@
     assert(!getIndex()->isRematerializable());
   }
 
   AssemblerFixup *Fixup = nullptr;
   // Determine the offset (is it relocatable?)
   if (getOffset() != nullptr) {
     if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(getOffset())) {
       Disp += static_cast<int32_t>(CI->getValue());
     } else if (const auto *CR =
                    llvm::dyn_cast<ConstantRelocatable>(getOffset())) {
-      if (CR->getName() != "") {
-        const auto FixupKind =
-            (getBase() != nullptr || getIndex() != nullptr) ? FK_Abs : FK_PcRel;
-        const RelocOffsetT DispAdjustment = FixupKind == FK_PcRel ? 4 : 0;
-        Fixup = Asm->createFixup(FixupKind, CR);
-        Fixup->set_addend(-DispAdjustment);
-      }
+      const auto FixupKind =
+          (getBase() != nullptr || getIndex() != nullptr) ? FK_Abs : FK_PcRel;
+      const RelocOffsetT DispAdjustment = FixupKind == FK_PcRel ? 4 : 0;
+      Fixup = Asm->createFixup(FixupKind, CR);
+      Fixup->set_addend(-DispAdjustment);
       Disp = CR->getOffset();
     } else {
       llvm_unreachable("Unexpected offset type");
     }
   }
 
   // Now convert to the various possible forms.
   if (getBase() && getIndex()) {
     const bool NeedSandboxing = Target->needSandboxing();
     (void)NeedSandboxing;
@@ skipping 69 matching lines @@
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
 } // namespace X8664
 } // end of namespace Ice
 
 X86INSTS_DEFINE_STATIC_DATA(X8664, X8664::Traits)