Adds support for ARMv6.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
 #include "vm/runtime_entry.h"
 #include "vm/simulator.h"
 #include "vm/stack_frame.h"
 #include "vm/stub_code.h"
 
 // An extra check since we are assuming the existence of /proc/cpuinfo below.
 #if !defined(USING_SIMULATOR) && !defined(__linux__) && !defined(ANDROID)
 #error ARM cross-compile only supported on Linux
 #endif
 
 namespace dart {
 
 DEFINE_FLAG(bool, print_stop_message, true, "Print stop message.");
 DECLARE_FLAG(bool, inline_alloc);
 
-
 // Instruction encoding bits.
 enum {
   H   = 1 << 5,   // halfword (or byte)
   L   = 1 << 20,  // load (or store)
   S   = 1 << 20,  // set condition code (or leave unchanged)
   W   = 1 << 21,  // writeback base register (or leave unchanged)
   A   = 1 << 21,  // accumulate in multiply instruction (or not)
   B   = 1 << 22,  // unsigned byte (or word)
   D   = 1 << 22,  // high/lo bit of start of s/d register range
   N   = 1 << 22,  // long (or short)
@@ skipping 1414 matching lines @@
   if (Address::CanHoldLoadOffset(kWord, offset, &offset_mask)) {
     ldr(rd, Address(PP, offset), cond);
   } else {
     int32_t offset_hi = offset & ~offset_mask;  // signed
     uint32_t offset_lo = offset & offset_mask;  // unsigned
     // Inline a simplified version of AddImmediate(rd, PP, offset_hi).
     ShifterOperand shifter_op;
     if (ShifterOperand::CanHold(offset_hi, &shifter_op)) {
       add(rd, PP, shifter_op, cond);
     } else {
-      movw(rd, Utils::Low16Bits(offset_hi));
-      const uint16_t value_high = Utils::High16Bits(offset_hi);
-      if (value_high != 0) {
-        movt(rd, value_high, cond);
-      }
+      LoadLargeImmediate(rd, offset_hi, cond);

[regis, 2014/03/06 17:32:11]

I would simply call LoadImmediate here.

[zra, 2014/03/07 19:00:17]

Done.

       add(rd, PP, ShifterOperand(LR), cond);
     }
     ldr(rd, Address(rd, offset_lo), cond);
   }
 }
 
 
 void Assembler::LoadPoolPointer() {
   const intptr_t object_pool_pc_dist =
      Instructions::HeaderSize() - Instructions::object_pool_offset() +
      CodeSize() + Instr::kPCReadOffset;
   LoadFromOffset(kWord, PP, PC, -object_pool_pc_dist);
 }
 
 
 void Assembler::LoadObject(Register rd, const Object& object, Condition cond) {
   // Smis and VM heap objects are never relocated; do not use object pool.
   if (object.IsSmi()) {
     LoadImmediate(rd, reinterpret_cast<int32_t>(object.raw()), cond);
   } else if (object.InVMHeap()) {
     // Make sure that class CallPattern is able to decode this load immediate.
     const int32_t object_raw = reinterpret_cast<int32_t>(object.raw());
-    movw(rd, Utils::Low16Bits(object_raw), cond);
-    const uint16_t value_high = Utils::High16Bits(object_raw);
-    if (value_high != 0) {
-      movt(rd, value_high, cond);
-    }
+    LoadLargeImmediate(rd, object_raw, cond);

[regis, 2014/03/06 17:32:11]

ditto

[zra, 2014/03/07 19:00:17]

Done.

   } else {
     // Make sure that class CallPattern is able to decode this load from the
     // object pool.
     const int32_t offset =
         Array::data_offset() + 4*AddObject(object) - kHeapObjectTag;
     LoadWordFromPoolOffset(rd, offset, cond);
   }
 }
 
 
@@ skipping 158 matching lines @@
   return (inst & ~kBranchOffsetMask) | offset;
 }
 
 
 int Assembler::DecodeBranchOffset(int32_t inst) {
   // Sign-extend, left-shift by 2, then add 8.
   return ((((inst & kBranchOffsetMask) << 8) >> 6) + Instr::kPCReadOffset);
 }
 
 
-static int32_t DecodeLoadImmediate(int32_t movt, int32_t movw) {
+static int32_t DecodeARMv7LoadImmediate(int32_t movt, int32_t movw) {
   int32_t offset = 0;
   offset |= (movt & 0xf0000) << 12;
   offset |= (movt & 0xfff) << 16;
   offset |= (movw & 0xf0000) >> 4;
   offset |= movw & 0xfff;
   return offset;
 }
 
 
+static int32_t DecodeARMv6LoadImmediate(int32_t mov, int32_t or1,
+                                        int32_t or2, int32_t or3) {
+  int32_t offset = 0;
+  offset |= (mov & 0xff) << 24;
+  offset |= (or1 & 0xff) << 16;
+  offset |= (or2 & 0xff) << 8;
+  offset |= (or3 & 0xff);
+  return offset;
+}
+
+
 class PatchFarBranch : public AssemblerFixup {
  public:
   PatchFarBranch() {}
 
   void Process(const MemoryRegion& region, intptr_t position) {
+    if (TargetCPUFeatures::arm_version() == ARMv6) {
+      ProcessARMv6(region, position);
+    } else {
+      ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
+      ProcessARMv7(region, position);
+    }
+  }
+
+ private:
+  void ProcessARMv6(const MemoryRegion& region, intptr_t position) {
+    const int32_t mov = region.Load<int32_t>(position);
+    const int32_t or1 = region.Load<int32_t>(position + 1*Instr::kInstrSize);
+    const int32_t or2 = region.Load<int32_t>(position + 2*Instr::kInstrSize);
+    const int32_t or3 = region.Load<int32_t>(position + 3*Instr::kInstrSize);
+    const int32_t bx = region.Load<int32_t>(position + 4*Instr::kInstrSize);
+
+    if (((mov & 0xffffff00) == 0xe3a0c400) &&  // mov IP, (byte3 rot 4)
+        ((or1 & 0xffffff00) == 0xe38cc800) &&  // orr IP, IP, (byte2 rot 8)
+        ((or2 & 0xffffff00) == 0xe38ccc00) &&  // orr IP, IP, (byte1 rot 12)
+        ((or3 & 0xffffff00) == 0xe38cc000)) {  // orr IP, IP, byte0
+      const int32_t offset = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
+      const int32_t dest = region.start() + offset;
+      const int32_t dest0 = (dest & 0x000000ff);
+      const int32_t dest1 = (dest & 0x0000ff00) >> 8;
+      const int32_t dest2 = (dest & 0x00ff0000) >> 16;
+      const int32_t dest3 = (dest & 0xff000000) >> 24;
+      const int32_t patched_mov = 0xe3a0c400 | dest3;
+      const int32_t patched_or1 = 0xe38cc800 | dest2;
+      const int32_t patched_or2 = 0xe38ccc00 | dest1;
+      const int32_t patched_or3 = 0xe38cc000 | dest0;
+
+      region.Store<int32_t>(position + 0 * Instr::kInstrSize, patched_mov);
+      region.Store<int32_t>(position + 1 * Instr::kInstrSize, patched_or1);
+      region.Store<int32_t>(position + 2 * Instr::kInstrSize, patched_or2);
+      region.Store<int32_t>(position + 3 * Instr::kInstrSize, patched_or3);
+      return;
+    }
+
+    // If the offset loading instructions aren't there, we must have replaced
+    // the far branch with a near one, and so these instructions
+    // should be NOPs.
+    ASSERT((or1 == Instr::kNopInstruction) &&
+           (or2 == Instr::kNopInstruction) &&
+           (or3 == Instr::kNopInstruction) &&
+           (bx == Instr::kNopInstruction));
+  }
+
+
+  void ProcessARMv7(const MemoryRegion& region, intptr_t position) {
     const int32_t movw = region.Load<int32_t>(position);
     const int32_t movt = region.Load<int32_t>(position + Instr::kInstrSize);
     const int32_t bx = region.Load<int32_t>(position + 2 * Instr::kInstrSize);
 
     if (((movt & 0xfff0f000) == 0xe340c000) &&  // movt IP, high
         ((movw & 0xfff0f000) == 0xe300c000)) {   // movw IP, low
-      const int32_t offset = DecodeLoadImmediate(movt, movw);
+      const int32_t offset = DecodeARMv7LoadImmediate(movt, movw);
       const int32_t dest = region.start() + offset;
       const uint16_t dest_high = Utils::High16Bits(dest);
       const uint16_t dest_low = Utils::Low16Bits(dest);
       const int32_t patched_movt =
           0xe340c000 | ((dest_high >> 12) << 16) | (dest_high & 0xfff);
       const int32_t patched_movw =
           0xe300c000 | ((dest_low >> 12) << 16) | (dest_low & 0xfff);
 
       region.Store<int32_t>(position, patched_movw);
       region.Store<int32_t>(position + Instr::kInstrSize, patched_movt);
       return;
     }
 
     // If the offset loading instructions aren't there, we must have replaced
-    // the far branch with a near one, and so these instructions should be NOPs.
+    // the far branch with a near one, and so these instructions
+    // should be NOPs.
     ASSERT((movt == Instr::kNopInstruction) &&
            (bx == Instr::kNopInstruction));
   }
 
   virtual bool IsPointerOffset() const { return false; }
 };
 
 
 void Assembler::EmitFarBranch(Condition cond, int32_t offset, bool link) {
-  const uint16_t low = Utils::Low16Bits(offset);
-  const uint16_t high = Utils::High16Bits(offset);
   buffer_.EmitFixup(new PatchFarBranch());
-  movw(IP, low);
-  movt(IP, high);
+  if (TargetCPUFeatures::arm_version() == ARMv6) {
+    LoadLargeImmediate(IP, offset);
+  } else {
+    ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
+    const uint16_t low = Utils::Low16Bits(offset);
+    const uint16_t high = Utils::High16Bits(offset);
+    movw(IP, low);
+    movt(IP, high);

[regis, 2014/03/06 17:32:11]

Call LoadPatchableImmediate independently of the arm version.
LoadPatchableImmediate then checks the arm version.

[zra, 2014/03/07 19:00:17]

Done.

+  }
   if (link) {
     blx(IP, cond);
   } else {
     bx(IP, cond);
   }
 }
 
 
 void Assembler::EmitBranch(Condition cond, Label* label, bool link) {
   if (label->IsBound()) {
@@ skipping 10 matching lines @@
       EmitFarBranch(cond, dest, link);
     } else {
       // Use the offset field of the branch instruction for linking the sites.
       EmitType5(cond, label->position_, link);
     }
     label->LinkTo(position);
   }
 }
 
 
-void Assembler::Bind(Label* label) {
+void Assembler::BindARMv6(Label* label) {
   ASSERT(!label->IsBound());
   intptr_t bound_pc = buffer_.Size();
   while (label->IsLinked()) {
     const int32_t position = label->Position();
     int32_t dest = bound_pc - position;
     if (use_far_branches() && !CanEncodeBranchOffset(dest)) {
       // Far branches are enabled and we can't encode the branch offset.
 
       // Grab instructions that load the offset.
+      const int32_t mov =
+          buffer_.Load<int32_t>(position);
+      const int32_t or1 =
+          buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
+      const int32_t or2 =
+          buffer_.Load<int32_t>(position + 2 * Instr::kInstrSize);
+      const int32_t or3 =
+          buffer_.Load<int32_t>(position + 3 * Instr::kInstrSize);
+
+      // Change from relative to the branch to relative to the assembler
+      // buffer.
+      dest = buffer_.Size();
+      const int32_t dest0 = (dest & 0x000000ff);
+      const int32_t dest1 = (dest & 0x0000ff00) >> 8;
+      const int32_t dest2 = (dest & 0x00ff0000) >> 16;
+      const int32_t dest3 = (dest & 0xff000000) >> 24;
+      const int32_t patched_mov = 0xe3a0c400 | dest3;
+      const int32_t patched_or1 = 0xe38cc800 | dest2;
+      const int32_t patched_or2 = 0xe38ccc00 | dest1;
+      const int32_t patched_or3 = 0xe38cc000 | dest0;
+
+      // Rewrite the instructions.
+      buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize, patched_mov);
+      buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize, patched_or1);
+      buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize, patched_or2);
+      buffer_.Store<int32_t>(position + 3 * Instr::kInstrSize, patched_or3);
+      label->position_ = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
+    } else if (use_far_branches() && CanEncodeBranchOffset(dest)) {
+      // Grab instructions that load the offset, and the branch.
+      const int32_t mov =
+          buffer_.Load<int32_t>(position);
+      const int32_t or1 =
+          buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
+      const int32_t or2 =
+          buffer_.Load<int32_t>(position + 2 * Instr::kInstrSize);
+      const int32_t or3 =
+          buffer_.Load<int32_t>(position + 3 * Instr::kInstrSize);
+      const int32_t branch =
+          buffer_.Load<int32_t>(position + 4 * Instr::kInstrSize);
+
+      // Grab the branch condition, and encode the link bit.
+      const int32_t cond = branch & 0xf0000000;
+      const int32_t link = (branch & 0x20) << 19;
+
+      // Encode the branch and the offset.
+      const int32_t new_branch = cond | link | 0x0a000000;
+      const int32_t encoded = EncodeBranchOffset(dest, new_branch);
+
+      // Write the encoded branch instruction followed by two nops.
+      buffer_.Store<int32_t>(position, encoded);
+      buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize,
+          Instr::kNopInstruction);
+      buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize,
+          Instr::kNopInstruction);
+      buffer_.Store<int32_t>(position + 3 * Instr::kInstrSize,
+          Instr::kNopInstruction);
+      buffer_.Store<int32_t>(position + 4 * Instr::kInstrSize,
+          Instr::kNopInstruction);
+
+      label->position_ = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
+    } else {
+      int32_t next = buffer_.Load<int32_t>(position);
+      int32_t encoded = Assembler::EncodeBranchOffset(dest, next);
+      buffer_.Store<int32_t>(position, encoded);
+      label->position_ = Assembler::DecodeBranchOffset(next);
+    }
+  }
+  label->BindTo(bound_pc);
+}
+
+
+void Assembler::BindARMv7(Label* label) {
+  ASSERT(!label->IsBound());
+  intptr_t bound_pc = buffer_.Size();
+  while (label->IsLinked()) {
+    const int32_t position = label->Position();
+    int32_t dest = bound_pc - position;
+    if (use_far_branches() && !CanEncodeBranchOffset(dest)) {
+      // Far branches are enabled and we can't encode the branch offset.
+
+      // Grab instructions that load the offset.
       const int32_t movw =
           buffer_.Load<int32_t>(position);

[regis, 2014/03/06 17:32:11]

You added  + 0 * Instr::kInstrSize below. For symmetry, you could add it here
too.

[zra, 2014/03/07 19:00:17]

Done.

       const int32_t movt =
           buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
 
-      // Change from relative to the branch to relative to the assembler buffer.
+      // Change from relative to the branch to relative to the assembler
+      // buffer.
       dest = buffer_.Size();
       const uint16_t dest_high = Utils::High16Bits(dest);
       const uint16_t dest_low = Utils::Low16Bits(dest);
       const int32_t patched_movt =
           0xe340c000 | ((dest_high >> 12) << 16) | (dest_high & 0xfff);
       const int32_t patched_movw =
           0xe300c000 | ((dest_low >> 12) << 16) | (dest_low & 0xfff);
 
       // Rewrite the instructions.
-      buffer_.Store<int32_t>(position, patched_movw);
+      buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize, patched_movw);
       buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize, patched_movt);
-      label->position_ = DecodeLoadImmediate(movt, movw);
+      label->position_ = DecodeARMv7LoadImmediate(movt, movw);
     } else if (use_far_branches() && CanEncodeBranchOffset(dest)) {
       // Far branches are enabled, but we can encode the branch offset.
 
       // Grab instructions that load the offset, and the branch.
       const int32_t movw =
           buffer_.Load<int32_t>(position);

[regis, 2014/03/06 17:32:11]

Here too? And below too? Not important.

[zra, 2014/03/07 19:00:17]

Done.

       const int32_t movt =
           buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
       const int32_t branch =
           buffer_.Load<int32_t>(position + 2 * Instr::kInstrSize);
 
       // Grab the branch condition, and encode the link bit.
       const int32_t cond = branch & 0xf0000000;
       const int32_t link = (branch & 0x20) << 19;
 
       // Encode the branch and the offset.
       const int32_t new_branch = cond | link | 0x0a000000;
       const int32_t encoded = EncodeBranchOffset(dest, new_branch);
 
       // Write the encoded branch instruction followed by two nops.
       buffer_.Store<int32_t>(position, encoded);
       buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize,
           Instr::kNopInstruction);
       buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize,
           Instr::kNopInstruction);
 
-      label->position_ = DecodeLoadImmediate(movt, movw);
+      label->position_ = DecodeARMv7LoadImmediate(movt, movw);
     } else {
       int32_t next = buffer_.Load<int32_t>(position);
       int32_t encoded = Assembler::EncodeBranchOffset(dest, next);
       buffer_.Store<int32_t>(position, encoded);
       label->position_ = Assembler::DecodeBranchOffset(next);
     }
   }
   label->BindTo(bound_pc);
 }
 
 
+void Assembler::Bind(Label* label) {
+  if (TargetCPUFeatures::arm_version() == ARMv6) {
+    BindARMv6(label);
+  } else {
+    ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
+    BindARMv7(label);
+  }
+}
+
+
 bool Address::CanHoldLoadOffset(OperandSize type,
                                 int32_t offset,
                                 int32_t* offset_mask) {
   switch (type) {
     case kByte:
     case kHalfword:
     case kUnsignedHalfword:
     case kWordPair: {
       *offset_mask = 0xff;
       return Utils::IsAbsoluteUint(8, offset);  // Addressing mode 3.
@@ skipping 189 matching lines @@
   LoadImmediate(IP, label->address(), cond);  // Address is never patched.
   bx(IP, cond);
 }
 
 
 void Assembler::BranchPatchable(const ExternalLabel* label) {
   // Use a fixed size code sequence, since a function prologue may be patched
   // with this branch sequence.
   // Contrarily to BranchLinkPatchable, BranchPatchable requires an instruction
   // cache flush upon patching.
-  movw(IP, Utils::Low16Bits(label->address()));
-  movt(IP, Utils::High16Bits(label->address()));
+  if (TargetCPUFeatures::arm_version() == ARMv6) {
+    LoadLargeImmediate(IP, label->address());
+  } else {
+    ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
+    movw(IP, Utils::Low16Bits(label->address()));
+    movt(IP, Utils::High16Bits(label->address()));
+  }

[regis, 2014/03/06 17:32:11]

LoadPatchableImmediate for both. LoadPatchableImmediate checks the arm version.

[zra, 2014/03/07 19:00:17]

Done.

   bx(IP);
 }
 
 
 void Assembler::BranchLink(const ExternalLabel* label) {
   LoadImmediate(IP, label->address());  // Target address is never patched.
   blx(IP);  // Use blx instruction so that the return branch prediction works.
 }
 
 
@@ skipping 18 matching lines @@
 
 
 void Assembler::BranchLinkOffset(Register base, int32_t offset) {
   ASSERT(base != PC);
   ASSERT(base != IP);
   LoadFromOffset(kWord, IP, base, offset);
   blx(IP);  // Use blx instruction so that the return branch prediction works.
 }
 
 
+void Assembler::LoadLargeImmediate(Register rd, int32_t value, Condition cond) {
+  if (TargetCPUFeatures::arm_version() == ARMv6) {

[regis, 2014/03/06 17:32:11]

See my comment in the header.

[zra, 2014/03/07 19:00:17]

Done.

+    // This sequence is patched in a few places, and should remain fixed.
+    const uint32_t byte0 = (value & 0x000000ff);
+    const uint32_t byte1 = (value & 0x0000ff00) >> 8;
+    const uint32_t byte2 = (value & 0x00ff0000) >> 16;
+    const uint32_t byte3 = (value & 0xff000000) >> 24;
+    mov(rd, ShifterOperand(4, byte3), cond);
+    orr(rd, rd, ShifterOperand(8, byte2), cond);
+    orr(rd, rd, ShifterOperand(12, byte1), cond);
+    orr(rd, rd, ShifterOperand(byte0), cond);
+  } else {
+    ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
+    movw(rd, Utils::Low16Bits(value), cond);
+    const uint16_t value_high = Utils::High16Bits(value);
+    if (value_high != 0) {
+      movt(rd, value_high, cond);
+    }
+  }
+}
+
+
 void Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
   ShifterOperand shifter_op;
   if (ShifterOperand::CanHold(value, &shifter_op)) {
     mov(rd, shifter_op, cond);
   } else if (ShifterOperand::CanHold(~value, &shifter_op)) {
     mvn(rd, shifter_op, cond);
   } else {
-    movw(rd, Utils::Low16Bits(value), cond);
-    const uint16_t value_high = Utils::High16Bits(value);
-    if (value_high != 0) {
-      movt(rd, value_high, cond);
-    }
+    LoadLargeImmediate(rd, value, cond);

[regis, 2014/03/06 17:32:11]

LoadDecodableImmediate

[zra, 2014/03/07 19:00:17]

Done.

   }
 }
 
 
 void Assembler::LoadSImmediate(SRegister sd, float value, Condition cond) {
   if (!vmovs(sd, value, cond)) {
     LoadImmediate(IP, bit_cast<int32_t, float>(value), cond);
     vmovsr(sd, IP, cond);
   }
 }
@@ skipping 145 matching lines @@
   vstrd(reg, Address(base, offset), cond);
 }
 
 
 void Assembler::AddImmediate(Register rd, int32_t value, Condition cond) {
   AddImmediate(rd, rd, value, cond);
 }
 
 
 void Assembler::AddImmediate(Register rd, Register rn, int32_t value,
-                            Condition cond) {
+                             Condition cond) {
   if (value == 0) {
     if (rd != rn) {
       mov(rd, ShifterOperand(rn), cond);
     }
     return;
   }
   // We prefer to select the shorter code sequence rather than selecting add for
   // positive values and sub for negatives ones, which would slightly improve
   // the readability of generated code for some constants.
   ShifterOperand shifter_op;
   if (ShifterOperand::CanHold(value, &shifter_op)) {
     add(rd, rn, shifter_op, cond);
   } else if (ShifterOperand::CanHold(-value, &shifter_op)) {
     sub(rd, rn, shifter_op, cond);
   } else {
     ASSERT(rn != IP);
     if (ShifterOperand::CanHold(~value, &shifter_op)) {
       mvn(IP, shifter_op, cond);
       add(rd, rn, ShifterOperand(IP), cond);
     } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) {
       mvn(IP, shifter_op, cond);
       sub(rd, rn, ShifterOperand(IP), cond);
     } else {
-      movw(IP, Utils::Low16Bits(value), cond);
-      const uint16_t value_high = Utils::High16Bits(value);
-      if (value_high != 0) {
-        movt(IP, value_high, cond);
-      }
+      LoadLargeImmediate(IP, value, cond);

[regis, 2014/03/06 17:32:11]

LoadDecodableImmediate

[zra, 2014/03/07 19:00:17]

Done.

       add(rd, rn, ShifterOperand(IP), cond);
     }
   }
 }
 
 
 void Assembler::AddImmediateSetFlags(Register rd, Register rn, int32_t value,
                                     Condition cond) {
   ShifterOperand shifter_op;
   if (ShifterOperand::CanHold(value, &shifter_op)) {
     adds(rd, rn, shifter_op, cond);
   } else if (ShifterOperand::CanHold(-value, &shifter_op)) {
     subs(rd, rn, shifter_op, cond);
   } else {
     ASSERT(rn != IP);
     if (ShifterOperand::CanHold(~value, &shifter_op)) {
       mvn(IP, shifter_op, cond);
       adds(rd, rn, ShifterOperand(IP), cond);
     } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) {
       mvn(IP, shifter_op, cond);
       subs(rd, rn, ShifterOperand(IP), cond);
     } else {
-      movw(IP, Utils::Low16Bits(value), cond);
-      const uint16_t value_high = Utils::High16Bits(value);
-      if (value_high != 0) {
-        movt(IP, value_high, cond);
-      }
+      LoadLargeImmediate(IP, value, cond);

[regis, 2014/03/06 17:32:11]

LoadDecodableImmediate

[zra, 2014/03/07 19:00:17]

Done.

       adds(rd, rn, ShifterOperand(IP), cond);
     }
   }
 }
 
 
 void Assembler::AddImmediateWithCarry(Register rd, Register rn, int32_t value,
                                      Condition cond) {
   ShifterOperand shifter_op;
   if (ShifterOperand::CanHold(value, &shifter_op)) {
     adc(rd, rn, shifter_op, cond);
   } else if (ShifterOperand::CanHold(-value - 1, &shifter_op)) {
     sbc(rd, rn, shifter_op, cond);
   } else {
     ASSERT(rn != IP);
     if (ShifterOperand::CanHold(~value, &shifter_op)) {
       mvn(IP, shifter_op, cond);
       adc(rd, rn, ShifterOperand(IP), cond);
     } else if (ShifterOperand::CanHold(~(-value - 1), &shifter_op)) {
       mvn(IP, shifter_op, cond);
       sbc(rd, rn, ShifterOperand(IP), cond);
     } else {
-      movw(IP, Utils::Low16Bits(value), cond);
-      const uint16_t value_high = Utils::High16Bits(value);
-      if (value_high != 0) {
-        movt(IP, value_high, cond);
-      }
+      LoadLargeImmediate(IP, value, cond);

[regis, 2014/03/06 17:32:11]

LoadDecodableImmediate

[zra, 2014/03/07 19:00:17]

Done.

       adc(rd, rn, ShifterOperand(IP), cond);
     }
   }
 }
 
 
 void Assembler::AndImmediate(Register rd, Register rs, int32_t imm,
                              Condition cond) {
   ShifterOperand op;
   if (ShifterOperand::CanHold(imm, &op)) {
@@ skipping 417 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM